By the way CGL stands for carry generation logic. I need this help urgently than

ID: 1814400 • Letter: B

Question

By the way CGL stands for carry generation logic. I need this help urgently thank you very much

The handout mentions two types of CGL, lookahead and ripple but only describes lookahead CGL. The ripple CGL would generate ci in terms of ci-1 as well as pi-1 and gi-1. Show the logic for that as a Verilog module. The module should have three 1-bit inputs, and a 1-bit output. Hint: To solve this problem draw a truth table with ai-1, bi-1, and ci-1 as inputs and gi-1, pi-1, and ci as outputs. Of course, you can easily fill in the g and p values. From this table you should be able to figure out a function for ci in terms of just ci-1, pi-1, and gi-1. WARNING: figure this out for yourself don't look for a solution elsewhere. The CLA handout does not (yet) provide a delay analysis for the hierarchical CLAs. Provide a delay analysis for a hierarchical CLA with lookahead CGL and a CLB-c (blocks use CLAs). Show both unrealistic and conservative delays. Provide a delay analysis for a hierarchical CLA with lookahead CGL and a CLB-r (blocks use ripple adders). Show both unrealistic and conservative delays. Provide a delay analysis for a hierarchical CLA with ripple CGL and a CLB-r (blocks use ripple adders). Show both unrealistic and conservative delays.