1. 1. (TCO 1) Write the VHDL ARCHITECTURE body for the circuit shown below. 2. W

Question

1. 1. (TCO 1) Write the VHDL ARCHITECTURE body for the circuit shown below.

2. Write the VHDL ARCHITECTURE file for the Y(3) output only for a 3-to-8 decoder using BIT_VECTOR signal types. The inputs are I0-I2 and the outputs are Y0-Y7answer. (Points : 10)

3. The diagram below shows an attempt to build a full-adder using two half adders (HA). Determine if the circuit is correct. Explain how you derived your answer.

4. In your own words, describe the difference between overflow and carry out for a 4-bit adder-subtractor circuit. (Points : 20)

Explanation / Answer

The last two bits of the carry row (reading right-to-left) contain vital information: whether the calculation resulted in an arithmetic overflow, a number too large for the binary system to represent (in this case greater than 8 bits). An overflow condition exists when these last two bits are different from one another. As mentioned above, the sign of the number is encoded in the MSB of the result."

So your example, when done in 4 bits, has an overflow, because the carry into the highest bit is 1, the carry out of it is 0. (Also easy to see intuitively: you start with two positive numbers and end with a negative number). You tried to make things a bit confusing by writing the result in 5 bits, but you omitted the carry out of the 3th bit. When done in 5 bits there is no overflow, because the last two carry bits (into and out of the 5th bit) are both .

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