Realize each of the following sets of functions using only a single 74154 decode
ID: 1809375 • Letter: R
Question
Realize each of the following sets of functions using only a single 74154 decoder module and output logic gates (choose NAND or AND gates to Minimize the fan in of the output gates). ( a) f1(a,b,c,d) = minterms(2,4,10,11,12,13) f2(a,b,c,d) = maxterms (0-3, 6-9, 12,14,15) f3(a,b,c,d) = b'c+a'b'd b) f1 (a,b,c,d) = Minterms(0,1,7,13) f2 (a,b,c,d) = Maxterms(0,1,2,5,6,7,8,9,11,12,15) f3 (a.b.c.d) = abc'+acd c) Repeat part (a) for the complements of the three functions d) Repeat part (b) for the complements of the three functionsExplanation / Answer
FOLLOW THIS THIS WILL HELP YOU Decoders are simply a collection of logic gates which are arranged in a specific way so as to breakdown any combination of inputs to a set of terms that are all set to '0' apart from one term. Therefore when one input changes, two output terms will change. Note that these terms are "minterms", remembering that minterms use a variable once, and once only. Lets say we have N inputs to a decoder, the number of outputs will be equal to 2^N. Thus there will be one line at the output for each possible input. Example: Decoder_1 In this example we will learn how a basic decoder works. A two to four line decoder is of the form, two inputs and four outputs. The Flash animation below shows how the inputs are decoded at each stage. Use the controls to stop the animation at any time. This diagram shows how a two to four line decoder works with a logic '1,0' on the input. So now we have the base logic diagram to show how a decoder makes use of simple logic to produce min terms of its input variables. To express a decoder on a schematic diagram is similar to the diagram for a multiplexor, just the opposite way round. The truth table for the considered example can be shown as follows. A B Y0 Y1 Y2 Y3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 Due to the way many logic IC's are made, it is ofter cheaper to purchase inverted decoders. These decoders use NAND gates instead of the AND gates we have seen in the decoder_1 example. In these cases the output to an inverted 2-4 line decoder would be like this: A B Y0 Y1 Y2 Y3 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 We will cover circuit implementation of both of these types of decoders in the next section of this chapter. It is worthy to note that decoders that are commonly available are 2-4 line, 3-8 line, and 4-10 line decoders. This has probably been made clear in your course notes. Before moving on to the next part of this chapter. Make sure you understand how decoders can be made from basic logic gates. (At least using AND gates and NOT gates). To test yourself, you may want to quickly draw the schematic diagram for a 3-8 line decoder, and the truth table. Then start thinking about how decoders can be used to implement functions. Example Decoder 2 To help get a decent understanding of how decoders work, you will find that a program called LabVIEW is available in the Electrical Engineering department. The link below is a LabVIEW demonstration that you can control. If nothing else, this demonstration will get you a little more familiar with the environment of LabVIEW for other examples later in the course. Using LabVIEW, open the following file to see an example of a 2 to 4 line decoder.
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