5. Given the Verilog code below, does it describe a Mealy or a Moore FSM? Type \
ID: 1716947 • Letter: 5
Question
5. Given the Verilog code below, does it describe a Mealy or a Moore FSM?
Type "Mealy" or "Moore"
module Test( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst ) begin
if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
end
2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end
end
2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;
end
end
default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule
//--------------------------------------------------------//
Answer : [A]
Explanation / Answer
A Mealy Machine is an FSM whose output depends on the present state as well as the present input.
Moore machine is an FSM whose outputs depend on only the present state.
in our example we have input inp and outout outp.
and also we have 3 different states. that is 00 , 01 , 10
if present state is 00 :
and if inp is 1 next state is 01 and outp is 0
and if inp is 0 next state is 10 and outp is 0
if present state is 01 :
and if inp is 1 next state is 00 and outp is 1
and if inp is 0 next state is 10 and outp is 0
if present state is 10 :
and if inp is 1 next state is 01 and outp is 0
and if inp is 0 next state is 00 and outp is 1
so it is clear that output outp is depends on present state and present input.
so this is a mealy FSM
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