Hi, can someone help me get this verilog code working for a 4 bit up counter. It

Question

Hi, can someone help me get this verilog code working for a 4 bit up counter. It must use the 3 modules( GatedDLatch, DFlipFlop, and Count4Up) with the headers exactly how I have them. I know theres simpler ways to implement this, but this is the task.

Here is my design code:

module Count4Up(input wire reset_n, input wire clk, output [3:0] q);

wire qn0, qn1, qn2, qn3;

DFlipFlop dff0(.reset_n(reset_n),.clk(clk),.q_n(qn0),.d(qn0),.q(q[0]));
DFlipFlop dff1(.reset_n(reset_n),.clk(qn0),.q_n(qn1),.d(qn1),.q(q[1]));
DFlipFlop dff2(.reset_n(reset_n),.clk(qn1),.q_n(qn2),.d(qn2),.q(q[2]));
DFlipFlop dff3(.reset_n(reset_n),.clk(qn2),.q_n(qn3),.d(qn3),.q(q[3]));

endmodule

module DFlipFlop
(
    input   wire       reset_n,
    input   wire       clk,
    input   wire       d,
    output   wire       q,
    output   wire       q_n
);

wire clk_n, qm, t;

not(clk_n, clk);

GatedDLatch Master(.d(d), .clk(clk_n), .q(qm), .q_n(t));
GatedDLatch Slave(.d(qm), .clk(clk), .q(q), .q_n(q_n));

endmodule

module GatedDLatch
(
    input   wire       clk,
    input   wire       d,
    output   wire       q,
    output   wire       q_n
);

wire s, r, dn;

not(dn, d);

nand(s, d, clk);
nand(r, dn, clk);

nand(q, q_n, s);
nand(q_n, q, r);


endmodule

And here is my testbench:

module testbench;
reg reset_n;
reg clk;
reg [3:0] q;
initial begin
    $dumpfile( "dump.vcd" );
    $dumpvars( 1, testbench );
  
    reset_n = 0;
   clk = 0;
    #3 $display(q);
    #15 $finish;
end
always
    #1 clk = ~clk;

Count4Up test
(
    .reset_n( reset_n ),
    .clk( clk ),
    .q( q )
);

endmodule

Explanation / Answer

module fourbit_upcount(Reset, Clock, E, Q);
input Reset, Clock, E;
output [3:0] Q;
reg [3:0] Q;
if (!Reset)
Q <= 0;
else if (E)
Q <= Q+1;

endmodule

module D_latch(D, Clk, Q);

input D, Clk;

output Q;

reg Q;

if (Clk)

Q = D;

endmodule

module flipflop(D, Clock, Resetn, Q);

input D, Clock, Resetn;

output Q;

reg Q;

if(!Resetn)

Q <= 0;

else

Q <= D;

endmodule

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