Design an Error Detector for Excess-3 decimal code. The output, F, is to be 1 if

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Design an Error Detector for Excess-3 decimal code. The output, F, is to be 1 iff the Excess-3 input represent an invalid code combination. Implement F in 2-levels using NAND gates only. Also implement F in 2-levels using NOR gates only. Using Verilog, re-implement the function F in Question 4 (using NAND and NOR). Your expected to submit your Verilog codes of the circuit as well as your testbench (for each implementation). Your are also expected to submit two snapshots of the output waveform for two input combinations (1) an output waveform when the input is a valid Ecess-3 code (2) an output waveform when the input is an invalid Ecess-3 code. For simplicity, assume all gate delays are negligible.

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