1. State the two minimum structures required to write a VHDL file and briefly de
ID: 1716517 • Letter: 1
Question
1. State the two minimum structures required to write a VHDL file and briefly describe each one
2. In VHDL what values do the predefined type BIT represent.
3. Write the Entity design declaration for the 74LS83 A full-adder.
4. Write te VHDL text file (entity and architecture) for a 2-input NAND gate.
5. Write the VHDL text file for a 2-input EX-OR gate.
6. write the VHDL text file for a 3-input NOR gate.
7. The VHDL file below does not correctly describe the logic expression Z = A + B*C. what is the error?
ENTITY nice_try IS
PORT (
A,B,C :IN BIT;
Z :OUT BIT);
END nice_try;
ARCHITECTURE model of nice_try IS
BEGIN
Z<= A or B and C;
END model;
8. Write the VHDL text file for the circuit shown below.
9. Explain VHDL concurrency
10. What is a VHDL assignment Operator? How is it different from the equal sign (=) operator?
Explanation / Answer
1)
An VHDL architecture can be implemented in different ways depending on its purpose.
Structural :
A structural implementation usually connects and instantiates other modules.
It serves to organize and connect modules together.
A structural implementation contains only other instantiated blocks wired together and also uses port maps.
Behavioral:
A behavioral implementation describes how a modules should function using the full array of VHDL constructs available.
Behaviorally designed modules are not necessarily synthesizable, but are useful for modeling and testing synthesizable modules.
Register Transfer :
A register transfer implementation describes the functionality of a design in terms of registers and the transfer of the data that flows between the registers.
Register transfer implementations are used to describe design that is to be synthesized on actual devices.
2)
In VHDL predefined type BIT represent values either 0 or 1.
3)
74ls83 is a 4 bit full adder find the entity as below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( a : in STD_LOGIC_VECTOR(3 down to 0);
b : in STD_LOGIC_VECTOR(3 down to 0);
cin : in STD_LOGIC;
sum: out STD_LOGIC_VECTOR(3 down to 0);
cout : out STD_LOGIC
);
end full_adder;
here a,b are 4 bit inputs , cin is a carry input ,cout is carry output and sum is 4 bit output .
4)
2 input nand gate :
5)
two input nor:
6)
library IEEE;
use IEEE.std_logic_1164.all;
entity NORGATE3 is
port(
x: in std_logic;
y: in std_logic;
z: in std_logic;
f: out std_logic);
end NORGATE3;
architecture behav of NORGATE3 is
signal a, b:std_logic;
begin
a<= x OR y;
b<= a OR z;
f<= NOT b;
end behav;
7)
find the correct code as below:
ENTITY nice_try IS
PORT (
A,B,C :IN STD_LOGIC;
Z :OUT STD_LOGIC);
END nice_try;
ARCHITECTURE model of nice_try IS
signal w : std_logic;
BEGIN
w<= B and C;
Z <= A or w;
END model;
here i have used in and out std_logic you can also use BIT
8)
Find the VHDL code as below:
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY rtl IS
PORT (
A,B,C,D :IN STD_LOGIC;
Y :OUT STD_LOGIC);
END rtl;
ARCHITECTURE model of rtl IS
signal e,f : std_logic;
BEGIN
e<= A and B;
f <= C and D;
Y <= e or f;
END model;
9)
One of the major VHDL characteristics is the concurrency.
Inside a VHDL architecture there is no specified order in the assignment statement. This means that if you exchange the order of two assignments the results is the same.
VHDL executes statements at the same time in parallel,as in Hardware.
for example :
inside architecture
is same as
10)
<= represents the assignment operator in VHDL
there is one basic difference between <= and = is <= is used to assign a value to the variable while = is used to check for equality.
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