Module C Verilog code is shown below. Read each of the following statement caref

Question

Module C Verilog code is shown below. Read each of the following statement carefully. If the entire statement is true in relation to Module C, circle T, otherwise circle F. T F Module C is a up/down counter T F 1-bit reset n input is to set the initial value of the module {output} to all zero. T F Both the reset n and the Id are synchronous input T F Upon (reset n is going from 1 right arrow 0), on the next positive edge of clock the output of Module B i.e. q if Id input is low, will change to 100

Explanation / Answer

Module C is a up/down counter this is True statement

1-bit reset_n input is to set the initial value of module to all zero this is false statement, If 1-bit reset_n input is to set the initial value of module to one (001)

Both the reset_n and ld are synchronous input this is True statement

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