This Circuit Uses 3 Modules (ALU adder/multiplier, D-Flip Flop, and Overflow Det

Question

This Circuit Uses 3 Modules (ALU adder/multiplier, D-Flip Flop, and Overflow Detect

Using VHDL, design each of the 3 modules (as shown above) to create the ALU addition/multiplication circuit above with the follwing conditions:

-Reset is asynchronous

-CLK and En to the register is synchronous

-A input is an unsigned constraint, i.e., (15 downto 0)

-Sel chooses the operation (+ or *) to be preformed by the ALU

Explanation / Answer

Adder Module: library ieee; use ieee.std_logic_1164.all; entity Full_Adder is port (X : in std_logic; Y : in std_logic; C_in : in std_logic; Sum : out std_logic ; C_out : out std_logic); end; architecture struc of Full_Adder is begin Sum RB(7 downto 0), C_out => C_out, Add_out => Add_out(7 downto 0) ); inst_Controller: Controller port map ( reset => reset, clk => clk, START => START, LSB => LSB, ADD_cmd => ADD_cmd, SHIFT_cmd => SHIFT_cmd, LOAD_cmd => LOAD_cmd, STOP => STOP ); inst_Multiplicand: Multiplicand port map ( reset => reset, A_in => A_in(7 downto 0), LOAD_cmd => LOAD_cmd, RA => RA(7 downto 0) ); inst_Multiplier_Result: Multiplier_Result port map ( reset => reset, clk => clk, B_in => B_in(7 downto 0), LOAD_cmd => LOAD_cmd, SHIFT_cmd => SHIFT_cmd, ADD_cmd => ADD_cmd, Add_out => Add_out(7 downto 0), C_out => C_out, RC => RC(15 downto 0), LSB => LSB, RB => RB(7 downto 0) ); end rtl; 4-bit ALU using VHDL entity ALU is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); z : out STD_LOGIC_VECTOR (3 downto 0); sel : in STD_LOGIC_VECTOR (3 downto 0); l : out STD_LOGIC_VECTOR (0 downto 0); g : out STD_LOGIC_VECTOR (0 downto 0); e : out STD_LOGIC_VECTOR (0 downto 0)); end ALU; architecture Behavioral of ALU is begin process (a,b,sel) is begin case sel is when "0000" => z z z z z z z z(3)

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