Scenario 9 21/01/16 Design for Test 2 Following your initial investigation into

Question

Scenario 9     21/01/16    Design for Test 2

Following your initial investigation into test equipment and its use you have become aware that increasing use of VLSI and SMT technology means that not all component faults can be detected with an In Circuit Tester. To improve this situation you have been advised to consider how effective testing can be achieved by making provision at the design stage. In particular you should:

Partition complex circuits to reduce testing effort.

Maximise access to inputs and outputs of complex devices so that the ICT can exert control and observe effects.

You already know that not all faults can be detected with one tester, hence your investigation into ICTs, MDAs and FTs. However, test equipment and its ongoing use cost money and it is important that testing is carried out economically as well as effectively. To specify capacities for your different testers will require more than knowledge of your overall unit throughput. You need to develop a test strategy that takes into account the effects of yield and ‘fault spectrum’ as well as purchase and running costs.

Guidance notes

Remember you do not necessarily have to solve the problem described. You do, however, need to understand and be able to explain how you would approach the problem.

Learning Outcomes

Following this PBL cycle you should be able to:

Question A: Explain why design should take into account testing requirements.

Question B: Discuss the use of partitioning to reduce test effort required.

Question C: Describe methods for ensuring controllability and observability when designing circuits for test.

Question D: Design an optimum test configuration (with equipment capacities) given information about product yield and fault spectrum.

Resources

Library Catalogue

Automatic Test Equipment                                                 Brindley

Testing Digital Circuits                                                        B.R.Wilkins

Advanced Simulation &Test Methodologies for VLSI   Russel & Sayers

IEEE Standard 1149.1

The Low Cost Board Test Handbook                               Craig Pynn

Strategies for Electronic Test                                             Craig Pynn

Digital Board Testing                                                           Bennets

Design to Test                                                                      Turino

Internet

http://www.checksum.com/analyst_ft.html

Other

DFM Lecture Notes on UniLearn

Explanation / Answer

Explain why design should take into account testing requirements

            Applying set of test stimuli to Inputs of circuit under test (CUT), and Analyzing          output responses

If incorrect (fail), CUT assumed to be faulty

If correct (pass), CUT assumed to be fault-free

Quality and economy are two major benefits of testing

The two attributes are greatly dependent and can not be defined without the other

Quality means satisfying the user’s needs at a minimum cost

The purpose of testing is to weed out all bad products before they reach the user

The number of bad products heavily affect the price of good products

A profound understanding of the principles of manufacturing and test is essential for an engineer to design a quality product

The testing problem

Given a set of faults in the circuit under test (or device under test), how do we obtain a certain (small) number of test patterns which guarantees a certain (high) fault coverage?

Test process

What faults to test? (fault modeling)

How are test pattern obtained? (test patternn generation)

How is test quality (fault coverage) measured?(fault simulation)?

How are test vectors applied and results evaluated?n (ATE/BIST)

2. Boundary value analysis and Equivalence partitioning

For a large circuit under test (CUT), it is likely that some test patterns result in excessive power dissipations that exceed the CUT's power rating. Designers may resort to low-power automatic test pattern generation (ATPG) tools to solve this problem, which, however, usually leads to larger test data volume and requires extra computational effort, even if such tools are available.

usually involves rerunning the time-consuming ATPG for each partitioned subcircuit and solving the problem of how to achieve an acceptable fault coverage for the glue logic between subcircuits

Equivalence Partitioning: This method is typically used to reduce the total number of test

3. Describe methods for ensuring controllability and observability when designing circuits for test.

Observability: ease of observing a node by watching external output pins of the chip

Controllability: ease of forcing a node to 0 or 1o by driving input pins of the chip

Reduces the cost of testing

Motivates design-for-test

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