1) a) The ISA is often referred to as the programmer’s model of the machine, why
ID: 1715189 • Letter: 1
Question
1)
a) The ISA is often referred to as the programmer’s model of the machine, why?
b) What is a machine language and what is an assembly language?
c) Write an ARC program (with necessary comments) to add an increment to the existing amount
Reserve a memory location for representing the water volume in a tank (say, maximum of 100), another memory location for I/O ( representing the amount of input, any value between 0 and 10). The program checks the input and if it is greater than 0, then add it to the current tank volume.
2)
(a) Explain the memory hierarchy, give the characteristics of each memory type in terms of access time, typical size and cost.
(b) What is DMA?
(c) How does cache memory work? Give an example of a direct mapped-cache scheme when there is a 232 word main memory which is divided in blocks of 26 words each block.
(d) When CPU needs data from memory, explain the policy of cache reach and write and how the performance of cache is evaluated.
3) What are the major steps in the execution of an instruction? Explain the datapath and its associated control signals for each of these major steps of instruction execution. Sketch a microarchitecture, with sufficient detail of both datapath and control units, to highlight the components that are involved in each instruction execution.
4)
a) Explain pipelining in datapath.
b) What happened if the pipeline cannot be filled? Give examples of such hazardous situations.
c) How would you compute the efficiency of pipelining?
Explanation / Answer
1). a) because it contains all the information that an assembly language programmer
needs to write the programs for that machine architecture. It consists all the instructions that the machine supports
b) Programming language that can be directly understood and obeyed by a machine (computer) without conversion (translation).
An assembly language (or assembler language) is a low-level programming language for a computer, or other programmable device
2. a).
· Level 0 (L0) Micro operations cache – 6 KiB [7] in size
· Level 1 (L1) Instruction cache – 128 KiB in size
· Level 1 (L1) Data cache – 128 KiB in size. Best access speed is around 700 GiB/second[8]
· Level 2 (L2) Instruction and data (shared) – 1 MiB in size. Best access speed is around 200 GiB/second[8]
· Level 3 (L3) Shared cache – 6 MiB in size. Best access speed is around 100 GB/second[8]
· Level 4 (L4) Shared cache – 128 MiB in size. Best access speed is around 40 GB/second[8]
· Main memory (Primary storage) – Gigabytes in size. Best access speed is around 10 GB/second.[8] In the case of aNUMA machine, access times may not be uniform
· Disk storage (Secondary storage) – Terabytes in size. As of 2013, best access speed is from a solid state drive is about 600 MB/second [9]
· Nearline storage (Tertiary storage) – Up to exabytes in size. As of 2013, best access speed is about 160 MB/second
b.) Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory (RAM) independently of the central processing unit (CPU).
c.) Let's take for example an action when the processor requests an information stored on the hard drive. Fetching information from the hard drive takes time, because hard drives are very sluggish in relation to the processor clock. Thus, every time information is retrieved, processing time is lost, although the requested information may be the same, over and over again.
The cache memory has the role of backing up the RAM. This means that before retrieving the information from the hard drive, the computer first looks for it in the cache memory. If it is present in the cache, then it is instantly relayed to the processor. This could quickly turn into a disadvantage if the requested information cannot be found in the cache, because processing time is first being lost by checking the cache, then actually retrieving the information from the hard drive.
The two processes are called 'cache hit' and 'cache miss', in case the requested information cannot be found in the cache memory. Usually, the cache maximum size is extremely small in relation to the large storage devices. However, with the help of multiple cache layers processing speed can be further improved.
3.) 1. Fetching the instruction: The next instruction is fetched from the memory address that is currently stored in theprogram counter (PC), and stored in the instruction register (IR). At the end of the fetch operation, the PC points to the next instruction that will be read at the next cycle.
2. Decode the instruction: During this cycle the encoded instruction present in the IR (instruction register) is interpreted by the decoder.
3. Read the effective address: In case of a memory instruction (direct or indirect) the execution phase will be in the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory, and any required data is fetched from main memory to be processed and then placed into data registers (Clock Pulse: T3). If the instruction is direct, nothing is done at this clock pulse. If this is an I/O instruction or a Register instruction, the operation is performed (executed) at clock Pulse.
4. Execute the instruction: The control unit of the CPU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The result generated by the operation is stored in the main memory, or sent to an output device. Based on the condition of any feedback from the ALU, Program Counter may be updated to a different address from which the next instruction will be fetched.
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