Write an SRC assembly code to work both multiplication (*) and division (/). Ope
ID: 673654 • Letter: W
Question
Write an SRC assembly code to work both multiplication (*) and division (/). Operands are defined as constants, and the operator is defined as an ASCII character as follows:
Character ASCII
* 42
/ 47
op1 * op2 OR op1 / op2
Your program must read first operand, the operator, and then the second operand as above. Store the result in the memory location for result. When the operation is division (/), the result is the integer part of the division (e.g., 9/4 = 2). If the second operand in division is zero, store -1 in the result.
You may start with the following template.
;
; CPE 221 HW 5
; date:
; student name:
; Multiplication and division (integer division) using addition and
; subtraction in SRC assembly language.
; If the second operand in division is zero, store -1 in the result.
;
.org 1000
ld r1, op1 ; r1 holds operand1
ld r2, op2 ; r2 holds operand2
ld r3, operator ; r3 holds the operator
lar r4, result ; r4 points to the location of result
lar r8, end
lar r10, multiplication
lar r12, division
addi r5,r3,-42 ; check for multiplication operation
brzr r10,r5 ; if yes, branch to multiplication
addi r5,r3,-47 ; check for division operation
brzr r12,r5 ; if yes, branch to division
br r8
multiplication:
lar r13, aa
lar r14, bb
lar r15, loop1
lar r16, store
la r20, 0 ; r20: number of negative values in op1 and op2
brpl r13,r1 ; check the sign of the first operand
neg r1,r1 ; if the sign is negative, make it to be positive
addi r20,r20,1
aa: ; DEFINE YOUR CODE ; check the sign of the second operand
; DEFINE YOUR CODE ; if the sign is negative, make it positive
; DEFINE YOUR CODE
bb: addi r22,r2, 0 ;save the second operand as counter
la r6, 0 ; sum is initialized to 0
loop1: add ; DEFINE YOUR CODE
addi ; DEFINE YOUR CODE ; decrement the value of r22
; DEFINE YOUR CODE ; if r22’s value is nonzero, go to loop1
addi r20, r20, -1 ; r20's possible value was 0, 1, or 2
brnz r16,r20 ; if r20 = 0,
neg ; DEFINE YOUR CODE ; one operand was negative and the other was positive
store: st ; DEFINE YOUR CODE
br ; DEFINE YOUR CODE
division:
Explanation / Answer
A computer understands machine code.
People (and compilers) write assembly language.
An assembler is a program (a very deterministic program). It translates each instruction to its machine code.
In the past, there was a one-to-one correspondence between assembly language instructions and machine language instructions.
This is no longer the case. Assemblers are now-a-days made more powerful, and can "rework" code, doing further translation on assembly language code in a manner that would once have been done only by a compiler.
The Translation of MAL to TAL
There are lots of MAL instructions that have no direct TAL equivalent. They will be translated (composed, synthesized) into one or more TAL instructions. The MAL instructions that need to be translated are often called pseudoinstructions.
How to determine whether an instruction is a TAL instruction or not: look in the list of TAL instructions. If the instruction is there, then it is a TAL instruction!
The assembler takes (non MIPS, or pseudoinstructions) MAL instructions and synthesizes them with 1 or more MIPS instructions. Here are a bunch of examples.
Multiplication and Division Instructions
becomes
Why? 32-bit multiplication produces a 64-bit result. To deal with this larger result, the MIPS architecture has 2 registers that hold results for integer multiplication and division. They are called HI and LO. Each is a 32 bit register.
mult places the least significant 32 bits of its result into LO, and the most significant into HI. Note that this can lead to an incorrect product being used as the result, in the case that more than 32 bits are required to represent the correct product.
Then, more TAL instructions are needed to move data into or out of registers HI and LO:
Data is moved into or out of register HI or LO.
One operand is needed to tell where the data is coming from or going to.
Integer division also uses register HI and LO, since it generates both a quotient and remainder as a result.
becomes
and
becomes
Load and Store Instructions
becomes
which becomes
or
Note that this 2-instruction sequence only works if the most significant bit of the LSpart of label is a 0.
The la instruction is also a pseudoinstruction (MAL, but not TAL). Its synthesis is accomplished with the 2 instruction sequence of lui followed by ori as given above. The lui instruction places the most significant 16 bits of the desired address into a register, and the ori sets the least significant 16 bits of the register. For example, assume that the label X has been assigned by the assembler to be the address 0xaabb00cc. The MAL instruction
becomes
A store instruction which implies the use of a la pseudoinstruction in its synthesis needs to place the address in a register. For example, consider the code
This synthesis may not use register $12 as the place to temporarily hold the address of X as the above example for the lw did. Using $12 would overwrite the value that is to be stored to memory. In this case, and other cases like this, the assember requires the use of an extra register to complete the synthesis. Register $1 on the MIPS processor is set aside (by convention) for exactly this type of situation. The synthesis for this sw example becomes
Instructions with Immediates
Instructions with immediates are synthesized with instructions that must have an immediate value as the last operand.
becomes
An add instruction requires 3 operands in registers. addi has one operand that must be an immediate.
These instructions are classified as immediate instructions. On the MIPS, they include: addi, addiu, andi, lui, ori, xori.
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