Write in Verilog. You will be developing a 4 bit basic ALU that will perform 4 b

Question

Write in Verilog.

You will be developing a 4 bit basic ALU that will perform 4 bit addition and 4 bit bitwise logic operations: NOT, AND, OR, XOR.

Here are some rules for the project:

1. You must name the ALU module and the connections must be in this order: 4bitALU(C, O, A, B, Switch)

(a) C is 1 bit output that is used for the carry bit

(b) O is 4 bit output that is used for the output

(c) A is 4 bit input that is the first term (i.e. A + B = CO)

(d) B is 4 bit input that is the second term (i.e. A + B = CO) (e) Switch is 4 bit input that controls which operation will be output

2. Switch = 0000 performs bitwise NOT operation on A and outputs it, carry bit is don’t care state

3. Switch = 0001 performs bitwise AND operation on A and B and outputs it, carry bit is don’t care state

4. Switch = 0010 performs bitwise OR operation on A and B and outputs it, carry bit is don’t care state

5. Switch = 0011 performs bitwise XOR operation on A and B and outputs it, carry bit is don’t care state

6. Switch = 1000 performs binary addition on A and B and outputs it along with proper carry bit

Explanation / Answer

module alu (op,a,b,CLogic); //module for simple ALU

output reg [3:0] op; //alu output
input [3:0] a,b; //Here inputs
input [1:0] CLogic;

always @(*)
//switch case
begin
case (CLogic)
0000 : begin op = ~a; $display("NOT operation"); end
0001 : begin op = a & b; $display("AND operation"); end
0010 : begin op = a || b; $display("OR operation"); end
0011 : begin op = a ^ b; $display("Logical XOR operation"); end
1000 : begin op = a + b; $display("Addition operation"); end
endcase //end switch statement
end
endmodule

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