Hello, I need help with these verilog code problems. These are instructions to u

Question

Hello, I need help with these verilog code problems. These are instructions to use on the verilog code below. For problems one and two, it asked you to change the code under /// Replace module below with solution. Please show steps on how it's done.

Problem 0: Run the testbench on the unmodified file. There should be errors on all but the min_4 (Four-element) module. Try modifying min_4 so that it simulates but produces the wrong answer. Re-run the simulator and verify that it’s broken. Then fix it.

Problem 1: Module min_n has an elt_bits-bit output elt_min and an elt_count element array of elt_bits-bit elements, elts. Complete min_n so that elt_min is set to the minimum of element in elts, interpreting the elements as unsigned integers. Do so using a linear connection of min_2 modules instantiated with a genvar loop. (A linear connection means that the output of instance i is connected to the input of instance i + 1.) Verify correct functioning using the testbench.

Problem 2: Module min_t is to have the same functionality as min_n. Complete min_t so that it recursively instantiates itself down to some minimum size. The actual comparison should be done by a min_2 module. Verify correct functioning using the testbench.

Problem 3: By default the synthesis script will synthesize each module for two array sizes, four elements and eight elements. (a) Run the synthesis script unmodified (use the command rc -files syn.tcl. Explain the differences in performance between the different modules. (b) Modify and re-run the synthesis script so that it synthesizes the modules with elt_bits set to 1. The synthesis program should do a better job on the behavioral and linear models. Why do you think that is? Hint: The 1-bit minimum module is equivalent to another common logic component that the synthesis program can handle well.

I have the verilog code below. This isn't all one code, each code is listed with each problem.

Any help is appreciated. Thanks.

Explanation / Answer

module min_b
#( int elt_bits = 4,
int elt_count = 8 )
( output logic [elt_bits-1:0] elt_min,
input wire [elt_bits-1:0] elts[elt_count] );

always @* begin

elt_min = elts[0];

for ( int i=1; iImplicit Structural 2-Input Minimum Module
//
module min_2
#( int elt_bits = 4 )
( output wire [elt_bits-1:0] elt_min,
input wire [elt_bits-1:0] elt_0,
input wire [elt_bits-1:0] elt_1 );

assign elt_min = elt_0 < elt_1 ? elt_0 : elt_1;

endmodule

/// Explicit Structural 4-Input Minimum Module
//
module min_4
#( int elt_bits = 4 )
( output wire [elt_bits-1:0] elt_min,
input wire [elt_bits-1:0] elts [4] );

wire [elt_bits-1:0] im1, im2;
min_2 #(elt_bits) m1( im1, elts[0], elts[1] );
min_2 #(elt_bits) m2( im2, elts[2], elts[3] );
min_2 #(elt_bits) m3( elt_min, im1, im2 );

endmodule

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