Hello, I need help with these verilog code problems. 0.) Run the testbench on th

Question

Hello, I need help with these verilog code problems.

0.) Run the testbench on the unmodified file. There should be errors on all but the min_4 (Four-element) module. Try modifying min_4 so that it simulates but produces the wrong answer. Re-run the simulator and verify that it’s broken. Then fix it.

1.) Module min_n has an elt_bits-bit output elt_min and an elt_count element array of elt_bits-bit elements, elts. Complete min_n so that elt_min is set to the minimum of element in elts, interpreting the elements as unsigned integers. Do so using a linear connection of min_2 modules instantiated with a genvar loop. (A linear connection means that the output of instance i is connected to the input of instance i + 1.) Verify correct functioning using the testbench.

2.) Module min_t is to have the same functionality as min_n. Complete min_t so that it recursively instantiates itself down to some minimum size. The actual comparison should be done by a min_2 module. Verify correct functioning using the testbench.

3.) By default the synthesis script will synthesize each module for two array sizes, four elements and eight elements. (a) Run the synthesis script unmodified (use the command rc -files syn.tcl. Explain the differences in performance between the different modules. (b) Modify and re-run the synthesis script so that it synthesizes the modules with elt_bits set to 1. The synthesis program should do a better job on the behavioral and linear models. Why do you think that is? Hint: The 1-bit minimum module is equivalent to another common logic component that the synthesis program can handle well.

I have the verilog code below

Any help is appreciated. Thanks.

Explanation / Answer

module testbench;

testbench_sz #(1,4) t0();
testbench_sz #(4,4) t1();
testbench_sz #(8,32) t2();
testbench_sz #(7,17) t3();

endmodule

module testbench_sz
#( int elt_bits = 8,
int elt_count = 80 );

localparam int mut_cnt_max = 5;

logic [elt_bits-1:0] elts[elt_count];

wire [elt_bits-1:0] elt_m[mut_cnt_max];
struct { int err_cnt = 0; int idx; } md[string];

min_b #(elt_bits,elt_count) m0(elt_m[0],elts);
min_n #(elt_bits,elt_count) m1(elt_m[1],elts);
if ( elt_count == 4 )
min_4 #(elt_bits) m2(elt_m[2],elts);

min_t #(elt_bits,elt_count) m3(elt_m[3],elts);

localparam int num_tests = 10000;

initial begin

md["Linear Generate"].idx = 1;
md["Tree Generate"].idx = 3;
if ( elt_count == 4 )
md["Four-Element"].idx = 2;

for ( int i=0; i<num_tests; i++ ) begin

for ( int j=0; j<elt_count; j++ ) elts[j] = $random();

#1;

foreach ( md[mut] ) begin

if ( elt_m[0] !== elt_m[md[mut].idx] ) begin

md[mut].err_cnt++;
if ( md[mut].err_cnt < 5 )
$write("Error test %0d for %s, 0x%x != 0x%x (correct) ",
i, mut, elt_m[md[mut].idx], elt_m[0] );
end

end

end

foreach ( md[mut] )
$write("Tests completed for %s at %0d x %0d, error count %0d ",
mut, elt_bits, elt_count, md[mut].err_cnt );

end

endmodule

// cadence translate_on

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