Note: Kindly write a complete andswer and i\'ll give you a positive feedback, th

Question

Note: Kindly write a complete andswer and i'll give you a positive feedback, thank

One difference between a write-through cache and a write-back cache (both with write- allocate) can be in the time it takes to write. During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) cycle we actually write the data. Let?s assume that 50% of the blocks are dirty for a write-back cache. For the question, assume that the write buffer for write through will never stall the CPU (no penalty). Assume that a cache read hit takes 1 clock cycle, the cache miss penalty is 50 clock cycles, and a block write from the cache to main memory takes 50 clock cycles (hint. this means there is no write buffer in write-back cache). Assume that the CPI for all other instructions is 1 without misses. Finally, assume the instruction cache miss rate is 0.5% and the data cache miss rate is 1%. a. Suppose that the average percentages of loads and stores are 25% and 9%, respectively. Estimate the performance of a write-through cache with a two-cycle write versus a write- back cache with a two-cycle write for each of the programs. b. Do the am but this time assume the write-through cache pipelines the writes, so that a write hit takes just one clock cycle.

Explanation / Answer

Hi,

Below is the solution to your problem.

For both caches, the instruction cache miss rate is 0.5% and the penalty is 50 cycles. For both caches, the data cache miss rate is 1% but the penalties are different. In a write through cache, there is nothing dirty in the cache, and write throughs are serviced by the write buffer, which is infinitely large in this case. Thus for both loads and stores the penalty is the cache miss penalty which is 50 cycles.

Memory Stall Cycles Instruction = (0.5% × 50) + (fstores + floads)(1.0% × 50)

In a write back cache, a miss on either a load or a store can either simply replace a clean line in the block (50 cycles) or can knock out a dirty line (an additional 50 cycles, which happens 50% of the time).

Memory Stall Cycles Instruction = (0.5% × 50) + (fstores + floads)(1.0% × (50 + (50% × 50)))

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