Design and simulate a binaryripple counterwith the MOD equal to the last 2 digit

Question

Design and simulate a binaryripple counterwith the MOD equal to the last 2 digits (LSDs) of your PSU email address. (If the last 2 digits of your PSU email address is less than 6 or is any power of 2, then use MOD=50). For example, if the last 2 digits of your PSU email address is 73, then you should design and simulate a MOD73 counter (counts from 0 to 72, then repeats.). Example, if your PSU email address is XYZ5435, then you would design a MOD-35 counter. If your PSU email address is XYZ5432, then you would design a MOD-50 counter. If your PSU email address is XYZ2405, then you would design a MOD-50 counter. IN MY CASE MY EMAIL ENDS WITH 63

Use negative-edge triggered JK flip flops in your design and any other logic gates as needed. The output in Multisim should be set of binary LED indicators (be careful with labeling). Include timing diagrams (with reset) with markups (use Logic Analyzer). Include critical portions of the timing diagrams. Include timing diagram markups for 2 counts before the reset to 0, count=0, and 2 counts after the reset to 0. Show count values in both binary and in decimal. Label msb and lsb. For example, if you have to design a MOD 50 counter (count sequence 0 to 49) then you would show binary and decimal markups on timing diagram for counts 48, 49, 0, 1, 2.

Explanation / Answer

module ripple_carry_counter(q, clk, reset);
output [5:0] q;
input clk, reset;
T_FF tff0(q[0], clk, reset);
T_FF tff1(q[1], q[0], reset);
T_FF tff2(q[2], q[1], reset);
T_FF tff3(q[3], q[2], reset);

T_FF tff3(q[4], q[3], reset);

T_FF tff3(q[5], q[4], reset);

endmodule

module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule

module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q; always @(posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule

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