Verilog, Finite State Machine, JKFFs I need to implement these JK flipflops usin
ID: 662602 • Letter: V
Question
Verilog, Finite State Machine, JKFFs
I need to implement these JK flipflops using verilog and my code is below this picture. Please do fix my code as it gives wrong outputs. RG and RN are z1 and z0, respectively.
module jkff(
input clk, r, x1, x0,
output reg s0,
output reg s1
);
wire a1, a2, a3, a4, J1, K1, J0, K0;
assign a1=(x1||s0);
assign J1=(a1&&x0);
assign a2=(x1||!s0);
assign K1=(x0&&a2);
assign a3=(x1||x0);
assign J0=(a3&&!s1);
assign a4=(x1||s1);
assign K0=(a4&&x0);
always @(posedge clk or posedge r)
begin
if (r) begin
s1<=0;
end
else begin
case ({J1,K1})
2'b00: s1<=s1;
2'b01: s1<=1'b0;
2'b10: s1<=1'b1;
2'b11: s1<=~s1;
endcase
end
end
endmodule
and my main file is:
module main_file(
input r,
input x1,
input x0,
input clk,
output RN,
output RG
);
wire ss0, ss1, a1;
jkff i_jkff
(
.s0(ss0),
.s1(ss1)
);
assign a1=(!ss0||x1);
assign RN=(x0&&ss1&&a1);
assign RG=(x1&&ss1&&!ss0);;
endmodule
Explanation / Answer
module jkff( input clk, input r, input x1, input x0, output reg s0, output reg s1 ); wire a1; wire a2; wire a3; wire J1; wire K1; wire J0; wire K0; assign a1=(x0&&s0); assign J1=(a1||x1); assign a2=(x0&&!s0); assign K1=(x1||a2); assign J0=(x0&&!s1); assign a3=(x0&&s1); assign K0=(a3||x1); always @(posedge clk or posedge r) begin if (r) begin s1Related Questions
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