The objective of this lab is to design simulate and implement a register file. A
ID: 658120 • Letter: T
Question
The objective of this lab is to design simulate and implement a register file. All code must use IEEE std_logic. Use std_logic_vector wherever possible.
PART 1 Modelsim Simulation
The objective of this part is to develop a register file with 4 registers each 8-bit wide. It should be possible to read or write any selected register. It should have the following entity description:
entity RegFile is
port(DATAIN:in std_logic_vector(7 downto 0);
REGSEL:in std_logic_vector(1 downto 0);
RW,CLK:in std_logic;
DATAOUT:out std_logic_vector(7 downto 0));
end RegFile;
Follow these steps:
(i) First code the following components in behavioral style using std_logic
Explanation / Answer
library
IEEE;
use
IEEE.Std_Logic_1164.
all
;
entity
BitMod_Core
is
generic
(
InstancePath: String := "BitMod_Core:"); --
For assertions
port
(
--
System signals
Test0:
in
Std_ULogic; --
Test mode
Clk:
in
Std_ULogic; --
Master Clock
Reset_N:
in
Std_ULogic; --
Master Reset
--
Interface to internal registers
A:
in
Std_Logic_Vector(0
to
1); --
Address bus
CS_N:
in
Std_ULogic; --
Chip select
RW_N:
in
Std_ULogic; --
Read/write
D_In:
in
Std_Logic_Vector(0
to
7); --
Data bus input
D_Out:
out
Integer
range
0
to
255; --
Data bus output
DEnable:
out
Boolean; --
Data bus enable
--
Serial Interface
SClk:
in
Std_ULogic; --
Serial clock
SData:
in
Std_ULogic; --
Serial input
MData:
out
Std_ULogic); --
Serial output
end
BitMod_Core;
architecture
Behavioural
of
BitMod_Core
is
--
Local signal declarations.
begin
--
Implementation of all functionality driven by Clk
ClkRegion:
process
(Reset_N, Clk)
begin
if
Reset_N = '0'
then
--
Asynchronous reset of model
elsif
Rising_Edge(Clk)
then
--
Rising Clk edge region
elsif
Falling_Edge(Clk)
then
--
Falling Clk edge region
else
--
Check for unknown Clk value, since the model is not
-- being reset and neither rising nor falling Clk edge
-- is detected.
--
No assertions at start up of simulation
assert not
(Is_X(Clk)
and
(Now /= 0 ns))
report
InstancePath & " 'X' on Clk input"
severity
Error;
end if
;
end process
ClkRegion;
--
Implementation of asynchronous functionality
AsynchronousRegion:
process
(Reset_N, CS_N, RW_N)
begin
if
Reset_N = '0'
then
--
Asynchronous reset of model
else
Rising_Edge(CS_N)
then
--
Asynchronous behaviour related to CS_N
else
--
Asynchronous behaviour related to RW_N
end if
;
end process
AsynchronousRegion;
end
Behavioural;
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