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1. If there is a miss in the TLB how many I/O operations are executed? Justify y

ID: 653555 • Letter: 1

Question

1. If there is a miss in the TLB how many I/O operations are executed? Justify your answer.

2. Consider a paging system with the page table stored in memory.

If a memory reference takes 200 nanoseconds, how long does a paged memory reference take?

If we add associative registers (TLB), and 75 percent of all page-table references are found in the associative registers. What is the effective memory reference time? (Assume that finding a page-table entry in the associative memory takes zero time, if the entry is there.).

3.- Name the five fields of the page table and explain why do we need each one of them?

4- Consider the following segment table:

Segment       Base            Length

0                   219              600

1                  2300             14

2                   90                100

3                  1327             580

4                   1952              96

What are the physical addresses for the following logical addresses?

a. 0,430

b. 1,10

c. 2,500

d. 3,400

e. 4,112

Explanation / Answer

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1. If there is a miss in the TLB how many I/O operations are executed? Justify your answer.

Ans:
   A translation lookaside buffer (TLB) is a cache that memory management hardware uses to improve virtual address
   translation speed.
  
   The CAM (content-addressable memory) search key is the virtual address and the search result is a physical address. If the requested address
   is present in the TLB, the CAM search yields a match quickly and the retrieved physical address can be used to access memory.
   This is called a TLB hit.
  
   If the requested address is not in the TLB, it is a miss, and the translation proceeds by looking up the page
   table in a process called a page walk. The page walk requires a lot of time when compared to the processor speed,
   as it involves reading the contents of multiple memory locations and using them to compute the physical address.
   After the physical address is determined by the page walk, the virtual address to physical address mapping is entered into the TLB.

   And IO Operations is depends on the underlying architecture.
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2. Consider a paging system with the page table stored in memory.
   If a memory reference takes 200 nanoseconds, how long does a paged memory reference take?
  
Ans:

   2 memory accesses are required i.e page lookup followed by actual access
   => 2*200ns
   => 400ns
   Hence , Paged memory reference take total 400ns.
  
   If we add associative registers (TLB), and 75 percent of all page-table references are found
   in the associative registers. What is the effective memory reference time? (Assume that finding a page-table
   entry in the associative memory takes zero time, if the entry is there.).
Ans:
   Formula for calculating effective memory reference time is,
   => 75% * TLB hit-time + 25% * TLB miss-time
   => 75% * 200ns + 25% * 400ns
   => 150ns + 100ns
   => 250ns

  
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3.- Name the five fields of the page table and explain why do we need each one of them?
Ans:

   The five field of page table.
  
   1.Page Number: used as an index into a page table which contains base address of each page in physical memory.
   2.Page offset: combined with base address to define the physical memory address that is sent to the memory unit.
3.Page-table base register (PTBR): points to the page table.
4.Page-table length register (PRLR): indicates size of the page table.
5.TLBs- translation look-aside buffers (TLBs)

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4- Consider the following segment table:

   Segment       Base   Length
   0           219       600
   1           2300   14
   2           90       100
   3           1327   580
   4           1952   96
   What are the physical addresses for the following logical addresses?  
       a. 0,430
       b. 1,10
       c. 2,500
       d. 3,400
       e. 4,112
Ans:
   (a) 219 + 430 = 649
   (b) 2300 + 10 = 2310
   (c) illegal reference; traps to operating system
   (d) 1327 + 400 = 1727
   (e) illegal reference; traps to operating system
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