Design a controller to operate two separate sets of three traffic light signals,
ID: 649560 • Letter: D
Question
Design a controller to operate two separate sets of three traffic light signals, one for each direction.
I keep getting two errors that are
Error: Node instance "u0" instantiates undefined entity "ibuf" and
Error: Node instance "u1" instantiates undefined entity "bufg"
What is is that I am doing wrong and how can I fix it, here is my code and I am using Quartus II ver 9
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
entity stop is
port (CLK: in STD_LOGIC;
Hold: in STD_LOGIC;
RST: in STD_LOGIC;
EW1: out STD_LOGIC;
EW2: out STD_LOGIC;
NS1: out STD_LOGIC;
NS2: out STD_LOGIC);
end entity stop;
architecture stop_arch of stop is
component ibuf port(I: in std_logic;
O: out std_logic);
end component;
component bufg port(I: in std_logic;
O: out std_logic);
end component;
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (S0, S1, S2, S3, S4, S5, S6);
signal Sreg0: Sreg0_type;
signal Clear: STD_LOGIC;
signal RESET: STD_LOGIC;
signal COUNT: INTEGER range 0 to 128;
signal in_c, buf_c: std_logic;
begin
-- clock needs to be routed through the clock buffer
u0: ibuf port map(I => clk, O => in_c);
u1: bufg port map(I => in_c, O => buf_c);
--concurrent signal assignments
RESET <= (Clear or RST);
--diagram ACTIONS;
-- 4-bit synchronous counter with count enable,
-- asynchronous reset and synchronous load
-- CLK: in STD_LOGIC;
-- RESET: in STD_LOGIC;
-- COUNT: inout INTEGER range 0 to 15;
process (CLK, RESET)
begin
if RESET='1' then
COUNT <= 0;
elsif CLK='1' and CLK'event then
COUNT <= COUNT + 1;
end if;
end process;
Sreg0_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
Sreg0 <= S0;
else
case Sreg0 is
when S0 =>
Sreg0 <= S1;
when S1 =>
if Hold='0' then
Sreg0 <= S2;
else
Sreg0 <= S1;
end if;
when S2 =>
if COUNT=30 then
Sreg0 <= S3;
else
Sreg0 <= S2;
end if;
when S3 =>
if COUNT=34 then
Sreg0 <= S4;
else
Sreg0 <= S3;
end if;
when S4 =>
if Hold='0' then
Sreg0 <= S5;
else
Sreg0 <= S4;
end if;
when S5 =>
if COUNT=30 then
Sreg0 <= S6;
else
Sreg0 <= S5;
end if;
when S6 =>
if COUNT=34 then
Sreg0 <= S1;
else
Sreg0 <= S6;
end if;
when others =>
Sreg0 <= S0;
end case;
end if;
end if;
end process;
-- signal assignment statements for combinatorial outputs
NS1_assignment:
NS1 <= '1' when (Sreg0 = S1) else
'0' when (Sreg0 = S2) else
'0' when (Sreg0 = S3) else
'1' when (Sreg0 = S4) else
'1' when (Sreg0 = S5) else
'1' when (Sreg0 = S6) else
'0';
NS2_assignment:
NS2 <= '1' when (Sreg0 = S1) else
'0' when (Sreg0 = S2) else
'1' when (Sreg0 = S3) else
'1' when (Sreg0 = S4) else
'1' when (Sreg0 = S5) else
'1' when (Sreg0 = S6) else
'1';
EW1_assignment:
EW1 <= '1' when (Sreg0 = S1) else
'1' when (Sreg0 = S2) else
'1' when (Sreg0 = S3) else
'1' when (Sreg0 = S4) else
'0' when (Sreg0 = S5) else
'0' when (Sreg0 = S6) else
'0';
EW2_assignment:
EW2 <= '1' when (Sreg0 = S1) else
'1' when (Sreg0 = S2) else
'1' when (Sreg0 = S3) else
'1' when (Sreg0 = S4) else
'0' when (Sreg0 = S5) else
'1' when (Sreg0 = S6) else
'1';
Clear_assignment:
Clear <= '1' when (Sreg0 = S1) else
'0' when (Sreg0 = S2) else
'0' when (Sreg0 = S3) else
'1' when (Sreg0 = S4) else
'0' when (Sreg0 = S5) else
'0' when (Sreg0 = S6) else
'1';
end stop_arch;
Explanation / Answer
What ever I understand from your code is that
1. Either you have not created instance of u0 and u1
2. if you have crerated the instance you might not have initialised it.
Pl. do to get proper results
Thanks
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