26.) Find the total amount of memory, in the units requested, for each of the fo

Question

26.) Find the total amount of memory, in the units requested, for each of the following CPUs, given the size of the address buses:

(a) 16-bit address bus (in K)

(b) 24-bit address bus (in megs)

(c) 32-bit address bus (in megabytes and gigabytes)

(d) 48-bit address bus (in megabytes, gigabytes, and terabytes)

27.) Regarding the data bus and address bus, which is unidirectional and which is bidirectional?

28.) What is the difference in capacity between a 4M memory chip and 4M of computer memory?

29.) True or false. The more address pins, the more memory locations are inside the chip. (Assume that the number of data pins is fixed.)

30.) True or false. The more data pins, the more each location inside the chip will hold.

31.) True or false. The more data pins, the higher the capacity of the memory chip.

32.) True or false. The more data pins and address pins, the greater the capacity of the memory chip.

33.) The speed of a memory chip is referred to as its ________________.

34.) True or false. The price of memory chips varies according to capacity and speed.

35.) The main advantage of EEPROM over UV-EPROM is ________________.

36.) True or false. SRAM has a larger cell size than DRAM.

37.) Which of the following, EPROM, DRAM, or SRAM, must be refreshed periodically?

38.) Which memory is used for PC cache?

39.) Which of the following, SRAM, UV-EPROM, NV-RAM, or DRAM, is volatile memory?

40.) RAS and CAS are associated with which memory?

(a) EPROM

(b) SRAM

(c) DRAM

(d) all of the above

41.) Which memory needs an external multiplexer?

(a) EPROM

(b) SRAM

(c) DRAM

(d) all of the above

42.) Find the organization and capacity of memory chips with the following pins.

(a) EEPROM A0A14, D0D7

(b) UV-EPROM A0A12, D0D7

(c) SRAM A0A11, D0D7

(d) SRAM A0A12, D0D7

(e) DRAM A0A10, D0

(f) SRAM A0A12, D0

(g) EEPROM A0A11, D0D7

(h) UV-EPROM A0A10, D0D7

(i) DRAM A0A8, D0D3

(j) DRAM A0A7, D0D7

394043.

Find the capacity, address, and data pins for the following memory organizations.

(a) 16Kx8 ROM

(b) 32Kx8 ROM

(c) 64Kx8 SRAM

(d) 256Kx8 EEPROM

(e) 64Kx8 ROM

(f) 64Kx4 DRAM

(g) 1Mx8 SRAM

(h) 4Mx4 DRAM

(i) 64Kx8 NV-RAM

44.) Find the address range of the memory design in the diagram.

45.) Using NAND gates and inverters, design decoding circuitry for the address range 2000H2FFFH.

46.) Find the address range for Y0, Y3, and Y6 of the 74LS138 for the diagrammed design.

Diagram for Problem 44

47. Using the 74138, design the memory decoding circuitry in which the memory block controlled by Y0 is in the range 0000H to 1FFFH. Indicate the size of the memory block controlled by each Y.

48.) Find the address range for Y3, Y6, and Y7 in Problem 47.

Diagram for Problem 46

49.) Using the 74138, design memory decoding circuitry in which the memory block controlled by Y0 is in the 0000H to 3FFFH space. Indicate the size of the memory block controlled by each Y.

50.) Find the address range for Y1, Y2, and Y3 in Problem 49.

Explanation / Answer

26)

(a) 16-bit address bus (in K):

For 16-bit address bus, the total amount of memory required is 216 = 26 x 210 =26k = 64k bytes of addressable memory.

(b) 24-bit address bus (in megs):

For 24-bit address bus, the total amount of memory required is 224 = 24 x 220 =24 M= 16M bytes of addressable memory.

(c) 32-bit address bus (in megabytes and gigabytes):

For 32-bit address bus, the total amount of memory required is 232 = 22 x 230 = 4 gigabytes of addressable memory and 4096 megabytes.

(d) 48-bit address bus (in megabytes, gigabytes, and terabytes):

For 48-bit address bus, the total amount of memory required is 248 = 256 Tera = 262144 Giga = 268435456 Mega of addressable memory.

27.)

Answer: The address bus is the unidirectional and the data bus is the bidirectional. The data bus transfers the information between the microcontrollers or processor and main memory. It sends the data in both directions. The address bus sends the address of the data to the memory. The address bus does not receive the data from the memory. Therefore, the address bus is the unidirectional.

28.)

Answer:

The difference in capacity between a 4M memory chip and 4M of computer memory is the memory capacity of the memory chip is always indicated in bits like kilobits and megabits and the capacity of the computer memory is indicated in bytes. Here, the 4M memory chip capacity is given as 4 Megabits and the 4M computer memory capacity is given as 4 Megabytes.

29)

Answer: True.

If the number of address pins increase, the memory locations are also increases in the chip. For the number of memory locations from 1K to 256M, the number of address pins is between 10 and 28 pins.

30.)

Answer: False

The data present in the memory does not depends on the data pins. It depends on the design of the chip. Therefore, the statement is false.

31.)

Answer: If the number of data pins increases, the capacity of the memory chip is also increases. The number of bits at each location in the memory chip has equal to the number of data pins on the chip.

32.)

Answer: True.

If the number of data pins and address pins increases, the capacity of the memory chip is also increases. For n address pins, 2n words can be addressed.

33.)

Answer: Access time.

The access time refers to how long the memory chips transfers the data to or from the CPU. Therefore, the speed of a memory chip is referred to as its access time.

34.)

Answer: True.

If the capacity and speed of the memory chips is more, the efficiency and the internal hardware requirements are also increases and then the price of the memory chip increases.

35.)

Answer: The main advantage of EEPROM over UV-EPROM is the EEPROM can erase and reprogram individual words without removal from the circuit.

36.)

Answer: True.

The SRAM cells occupies more space than the DRAM cells in the memory and SRAM cells requires more hardware equipment. Therefore, the SRAM has a larger cell size than DRAM.

37.)

Answer:

The DRAM must be refreshed periodically. The DRAM is a volatile memory. As, the DRAM losses the data when the power is off, the data of the DRAM must be refreshed periodically. It has very high density and slower in speed.

38.)

Answer: The SRAM memory is used for the PC cache. As the SRAM memory is very fast and small size, the PC cache used the SRAM memory.

39.)

Answer: The SRAM and DRAM are the volatile memories. Both losses the data when the power is turned off. But, the UV-EPROM and NV-RAM are the non-volatile memories. These can retain the data when the power is turned off.

40.)

The RAS and CAS are associated with DRAM memory. The RAS and CAS are used in the refreshing process of the memory of the DRAM.

41.)

Answer: DRAM

The DRAM requires an external multiplexer. The multiplexer is used to produce the multiplexed address used by the DRAM memory.

42)

(a) EEPROM A0-A14, D0-D7

The number of address bits(A0-A14) is 15 bits

Then the memory capacity is 215 = 25 x 210 = 25K = 32 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 32 x 8 = 256 Kbits.

The number of data bits(D0-D7) is 8 bits.

Therefore, the capacity of memory chips 8bit data and 256 Kbits.

(b) UV-EPROM A0-A12, D0-D7

The number of address bits(A0-A12) is 13 bits

Then the memory capacity is 213 = 23 x 210 = 23K = 8 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 8x 8 = 64Kbits.

The number of data bits(D0-D7) is 8 bits.

Therefore, the capacity of memory chips 8bit data and 64 Kbits.

(c) SRAM A0-A11, D0-D7

The number of address bits(A0-A11) is 12 bits

Then the memory capacity is 212 = 22 x 210 = 22K = 4 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 4x 8 = 32Kbits.

The number of data bits(D0-D7) is 8 bits.

Therefore, the capacity of memory chips 8bit data and 32 Kbits.

(d) SRAM A0-A12, D0-D7

The number of address bits(A0-A12) is 13 bits

Then the memory capacity is 213 = 23 x 210 = 23K = 8 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 8x 8 = 64Kbits.

The number of data bits(D0-D7) is 8 bits.

Therefore, the capacity of memory chips 8bit data and 64 Kbits.

e) DRAM A0-A10, D0

The number of address bits(A0-A10) is 11 bits

Then the memory capacity is 211 = 21 x 210 = 21K = 2 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 2x 8 = 16Kbits.

The number of data bits(D0) is 1 bits.

Therefore, the capacity of memory chips 1bit data and 16 Kbits.

(f) SRAM A0-A12, D0

The number of address bits(A0-A12) is 13 bits

Then the memory capacity is 213 = 23 x 210 = 23K = 8 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 8x 8 = 64Kbits.

The number of data bits(D0) is 1 bits.

Therefore, the capacity of memory chips 1bit data and 64 Kbits.

(g) EEPROM A0-A11, D0-D7

The number of address bits(A0-A11) is 12 bits

Then the memory capacity is 212 = 22 x 210 = 22K = 4 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 4x 8 = 32Kbits.

The number of data bits(D0-D7) is 8 bits.

Therefore, the capacity of memory chips 8bit data and 32 Kbits.

(h) UV-EPROM A0-A10, D0-D7

The number of address bits(A0-A10) is 11 bits

Then the memory capacity is 211 = 21 x 210 = 21K = 2 KB(Kilobytes)

As 1 byte is 8 bits, the memory capacity is 2x 8 = 16Kbits.

The number of data bits(D0-D7) is 8 bits.

Therefore, the capacity of memory chips 8bit data and 16Kbits.

(i) DRAM A0-A8, D0-D3

The number of address bits(A0-A8) is 9 bits

Then the memory capacity is 29 bits = 512bits

The number of data bits(D0-D3) is 4 bits.

(j) DRAM A0-A7, D0-D7

The number of address bits(A0-A8) is 9 bits

Then the memory capacity is 29 bits = 512bits

The number of data bits(D0-D7) is 8 bits.

43)

(a) 16Kx8 ROM

Here, 16K = 16 * 1024 = 24 * 210 = 214 = 16384

"16K X 8" means that 16K locations and 8 bits per location.

Address pins/ Address lines:

Here memory chip has 16K locations/addresses i.e. 214 locations/addresses

Therefore, if there are 'n' address lines then there must be 2n addresses. So, 2n = 214 . Hence, n = 14 Address pins/Address lines.

Data pins/Data Lines:

The 8 bits of data for every location within 16K. Hence for loading addresses on address bus every time memory needs 8 data lines for data bus.

Capacity:

Therefore,16K locations with 8 bits for each location. Hence, capacity is (16 * 8) K bits = 128K bits OR 16K bytes.

(d) 256Kx8 EEPROM

Here, 256K = 256 * 1024 = 28* 210 = 218 = 262144

"256K X 8" means that 256K locations and 8 bits per location.

Address pins/ Address lines:

Here memory chip has 256K locations/addresses i.e. 218 locations/addresses

Therefore, if there are 'n' address lines then there must be 2n addresses. So, 2n = 218 . Hence, n = 18 Address pins/Address lines.

Data pins/Data Lines:

Here 8 bits of data for every location within 64K. Hence for loading addresses on address bus every time memory needs 8 data lines for data bus.

Capacity:

Therefore,256K locations with 8 bits for each location. Hence, capacity is (256 * 8) K bits = 2048K bits OR 256K bytes.

(e) 64Kx8 ROM

Here,64K = 64 * 1024 = 26* 210 = 216 = 65536

"64K X 8" means that 64K locations and 8 bits per location.

Address pins/ Address lines:

Here memory chip has 64K locations/addresses i.e. 216 locations/addresses

Therefore, if there are 'n' address lines then there must be 2n addresses. So, 2n = 216 . Hence, n = 16 Address pins/Address lines.

Data pins/Data Lines:

The 8 bits of data for every location within 64K. Hence for loading addresses on address bus every time memory needs 8 data lines for data bus.

Capacity:

Therefore, 64K locations with 8 bits for each location. Hence, capacity is (64 * 8) K bits = 512K bits OR 64K bytes.

(g) 1Mx8 SRAM

Here, 1M = 1024K = 1024 * 1024 = 210* 210 = 220= 1048576

"1024K X 8" means that 1024K locations and 8 bits per location.

Address pins/ Address lines:

Here memory chip has 1024K locations/addresses i.e. 220 locations/addresses

Therefore, if there are 'n' address lines then there must be 2n addresses. So, 2n = 220 . Hence, n = 20 Address pins/Address lines.

Data pins/Data Lines:

The 8 bits of data for every location within 1M = 1024K. Hence for loading addresses on address bus every time memory needs 8 data lines for data bus.

Capacity:

Therefore,1024K locations with 8 bits for each location. Hence, capacity is (1024 * 8) K bits = 8192K bits OR 1024K bytes.

44)

The address bits A0 to A13 is used to select the address, which is indicates AD in the diagram.
The binary values of the address start at 0 and end at 213-1
The address range in decimal: 0 to 213-1
The bits D0 to D7 are the digital outputs.
The bits A14 and A15 are used to for the CS signal, which is the Chip Select.

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