(3) In a personal computer, a disk controller is typically used to transfer a st
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Question
(3) In a personal computer, a disk controller is typically used to transfer a stream of bytes from a floppy disk drive to a memory buffer with the help of a host such as the central processing unit (CPU) or a direct memory access(DMA) controller. Figure E5.2 shows a partially completed and simplified state diagram for the control of the data transfer.
The controller signals the host each time a new byte is available. The data must then be read and stored before another byte is ready. When the disk controller senses the data has been read, it indicates that data is not available, in preparation for the next byte. If any byte is not read before the next one comes along, the disk controller asserts a data lost error signal until the disk controller is reset. Add the following to the diagram: reset, indicate data not available, indicate data available, data read by host, new data ready, indicate data lost.
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Explanation / Answer
In a typical computer system, a mass storage disk device is usually utilized to store data that are frequently transferred to or from the host system. In such data transfer processes between the host and the disk device, the operations are either a host write disk cycle or a host read disk cycle. Furthermore, to accommodate different data transfer characteristics of both the host and the disk, a buffer memory is commonly utilized to temporarily hold the data during the transfer process.
During the host read disk cycle for instance, the data recorded on the disk magnetic medium are sensed and transferred out through the disk controller to a buffer memory first and then further to the host when the host is ready to receive the data. During the host write disk cycle, data coming from the host are sent to the buffer memory first and then to the disk controller and finally enter into the disk.
In either direction of the data transfer cycle, a direct memory access (DMA) controller of the disk controller is used to control all transfer actions involved. First of all, the host accesses the buffer memory in units of data bytes while the data readout or written into the disk are in the units of sectors (512 bytes for example). Hence, the DMA controller must ascertain whether the buffer memory is empty or full when the host is to transfer data on the one hand, and to assure that there is a complete sector of data to be written into the disk. Also, the DMA controller must ensure that there is a full sector space available in the buffer memory for data to be read out from the disk.
Furthermore, the DMA controller generates address signals that are necessary for the host and the disk controller to access a specific buffer memory location so that the data can be transferred to or from the buffer memory. In addition, the DMA controller must prevent the host from reading data back from the disk when some errors have emerged and have not been corrected.
There are also well known implementations of different DMA control functions in several commercial disk controllers. For instance, Adaptec Inc.'s disk controller (AIC-610) incorporates a DMA controller which has pointers designated as write access, read access and stop pointers. The actual uses of the first two pointers depend upon which buffer port is selected and the direction of data transfer. The stop pointer is used to control data transfer between the host and the buffer. In this approach, transfer control processes are performed by the host, thereby reducing the host's performance.
The other known design of a DMA controller is Standard Microsystems Corp.'s disk controller (95CO2). In this device, the DMA controller is enhanced to a level equivalent to a microprocessor, including many internal registers, counters, a state machine and an ALU (arithmetic and logic unit). Its various counters include an offset counter to keep track of the empty/full condition in the buffer and an auxiliary offset counter to trace the number of error-free data bytes left in the buffer. Although the DMA controller allows disk data transfers without the intervention of the host, the controller itself requires much additional hardware and involves complex operations.
The object of this invention is to provide an effective DMA control function with minimum hardware requirements on the one hand and to cope with the complex buffer management task when data transferred between the host and the disk are different in data size and transfer speed.
This invention utilizes two primary pointers to indicate the addresses of the buffer memory accessed in the process of data transfer between the host and the disk. Two additional pointers with specific contents are designated in accordance with a predetermined relation with the two primary pointers. As data transfer progresses, these pointers are changed in content and compared to generate flag signals to activate a buffer memory port based on a predetermined operative rule.
By means of this arrangement, the DMA controller is enabled to detect whether the buffer memory is empty or full whenever the host is to transfer data. The disk starts to receive a full sector data from, or transfer data to, the buffer memory when a sector of data or an empty sector space is available respectively. The DMA controller is capable of accommodating different data transfer size and transferring good data when error data are corrected accordingly.
According to this invention, the DMA controller handles the data transfer in an automatic and efficient process without intervention of the host. And with the predetermined operative rule mentioned above, a data overrun situation in the buffer memory is prevented.
The operation of the disk controller 3 can be easily understood by observing the data transfer operation from the disk drive 2 (disk read operation) and data transfer operation into the disk drive 2 (disk write operation). In the disk read operation, the stored data in the disk (not shown) are read out and sent into the decoder 7 for decoding. The resulting serial data bits are then converted into parallel data bytes through the deserializer 19b. The data bytes are then computed with data from the sequence RAM 14 to determine a correct data sector I.D. and are sent into the ECC/CRC block 17 to check for errors incurred during the read back process.
In the disk write operation, the host interface 11 begins by sending a host cycle request to the priority resolver 15 to transfer data into the RAM buffer 4. Then, the RAM buffer 4 data are sent into the FIFO 16 by the FIFO 16 sending a FIFO cycle request to the priority resolver 15 until the FIFO 16 is full. Whenever the FIFO 16 is empty a FIFO cycle request is sent again. Concurrently, the data are also sent into the ECC/CRC 17 to generate check bytes for each sector. The data bytes in the FIFO 16 are first sent into the serializer 19a for converting the parallel data bytes into bit streams which are channel encoded through the encoder 7 to generate the desired data channel coding format such as MFM (modified frequency modulation) and RLL (run length limited) code. The encoded data are then written into the disk.
DISK CONTROLLER
(a) LuP Interface
The LuP interface 10 block takes care of communication between the disk controller 3 and the local microprocessor 6 of , which is a separate single chip microcomputer controlled by its stored program. When the LuP 6 needs to access the registers of the disk controller 3 or the RAM buffer 4, it communicates on CS pins (101), ALEB pins (102), AD 0-7 Port (107), RDB pins (104) or WRB pins (105) of the LuP interface 10 to set the disk controller's internal register or to generate a LuP cycle request. A INT pin 106 on the LuP Interface 10 is set by the disk controller 3 to inform the LuP 6 of the occurrence of events such as any ECC error at the ECC/CRC 17 or a sector ID error detected at the sequencer RAM 14. The AD 0-7 port (107) receives and transmits addresses and data to or from internal registers of the LuP 6.
(b) Host Interface
The Host Interface 11 generates signals such as Port H Req. B signal 3715 when the disk controller 3 needs to transfer data to or from the host. As each byte of data is transferred or received by the host 1, a Port H ACK B signal 3714 is sent by the host 1 to the Host Interface 11 to respond as a handshaking signal responsive to the Port H Req. B signal 3715. A LOI signal 3718 sent by the Host Interface 11 latches data at any external input/output data latch (not shown) in case of data loss. A BIEB signal 3716 and a BOEB signal 3717 control data flow to and from the RAM buffer 4.
(c) Peripheral Interface
The Peripheral Interface 13 provides a WG signal 132 to command the disk drive 2 to output a write current to its magnetic heads (during disk write operations) and an RG signal 131 to command a phase lock loop circuit in the disk drive 2 to lock on to incoming raw disk data played back from the disk (during disk read operations). The Peripheral Interface 13 is connected to the sequencer RAM 14 and the ECC/CRC 17.
(d) Sequencer RAM
The Sequencer RAM 14 coordinates the operational relationships among the various blocks of FIG. 2. The Sequencer RAM 14 is preferably constructed by using an array of RAM organized in multiple words each of which are further organized in multiple bytes. Each byte represents a field in sequence flow control. By programming these fields of each word, all operating sequences among all building blocks within the disk controller 3 can be implemented in the well known manner.
(e) ECC/CRC
This block 17 performs the generation of data check bytes (ECC encoding) in the disk write operation in accordance with selected ECC/CRC polynomials in the well known manner. When the disk controller 3 reads data back, these polynomials are also fed into this block to check if there is any error. If errors are detected, this block calculates the error location and the error pattern and then issues an ECC error interrupt to the LuP 6 to perform error correction ("ECC correction").
(f) FIFO Memory
The FIFO (first-in-first-out) Memory 16 accommodates different transfer rates between the disk 2 and the host 1. The size of the FIFO Memory 16 is programmable up to 16 bytes of memory and is dependent upon the data transfer rate of the disk drive 2, the data transfer rate of the host 1 and the RAM buffer access speed.
(g) Clock Control
The Clock Control 18 receives two independent clock inputs, namely a DMACLK 1 signal 181 and a RRC signal 182. The DMACLK1 signal 181 is the RAM buffer transfer clock governing the rate of data transfer between the buffer interface 12 and the host interface 11. The RRC signal 182 is the sequencer RAM operation clock governing the speed of the sequencer RAM 14 and is the FIFO transfer clock governing the rate of data transfer between the FIFO Memory 16 and the Peripheral Interface 13. These two clocks are independent so that the host data transfer rate is not throttled by the slower disk data transfer rate.
(h) Encoder/Decoder and Serializer/Deserializer
The serializer 19a and the deserializer 19b convert parallel byte data to serial bit stream data and vice-versa, respectively. The encoder/decoder 7 converts data into the desired data format before writing into the disk and recovers the data read from the disk to its original data format.
A preferred structure of the encoder/decoder 7 is disclosed in copending application, U.S. application Ser. No. 07/429/217 filed by the applicant on even date herewith, which is now a U.S. Pat. No. 5,028,922.
The operation rules described above can be generalized as follows: In initializing stages, all devices inside the DMAC 5 are set to the initial values. Whenever a data transfer is completed, relevant pointers are incremented and then compared to determine whether to activate the Port State Solver 36 to generate or reverse the Start Port D 38 or Stop Port H signals accordingly. All these operation rules apply to the host write disk as well as the host read disk cycles.
The operation of the DMA controller 5 thus constructed in cooperation with other blocks of the disk controller will result in desirable functions of data transfer between the host 1 and the disk 2. With the minimum requirement of the hardware, the DMA controller 5 can detect whether the buffer memory 4 is accessible by the host 1 and the disk 2 when a data transfer process starts. The controller 5 is capable of transferring data when error data are detected and corrected. Accordingly, the DMA controller 5 can efficiently handle data transfer without the intervention of the local processor 6 and the host 1 and therefore elevate the performance of the host system
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