H. Given a data cache with 4 blocks cach of 4x32-bit words, what would the hit r

Question

H. Given a data cache with 4 blocks cach of 4x32-bit words, what would the hit rate be for the cache when the following array accesses are made? Assume the cache is initially empty, that the processor operates on 32-bit integers and has a byte-addressed memory,a array a is at address 0. (2 points) and that the first element of int a[20] al0]: a[4]; al1]: a[0] a[5]; a13] a[0]: al1]: Hit Rate

Explanation / Answer

Using LRU algorithm: ----------------------- int a[20]; a[0]; # Cache Miss -> Cache [0] a[4]; # Cache Miss -> Cache [0, 4] a[12]; # Cache Miss -> Cache [0, 4, 12] a[1]; # Cache Miss -> Cache [0, 4, 12, 1] a[0]; # Cache Hit -> Cache [0, 4, 12, 1] a[5]; # Cache Miss -> Cache [0, 5, 12, 1] a[13]; # Cache Miss -> Cache [0, 5, 13, 1] a[17]; # Cache Miss -> Cache [0, 5, 13, 17] a[0]; # Cache Hit -> Cache [0, 5, 13, 17] a[1]; # Cache Miss -> Cache [0, 1, 13, 17] Cache Hit only 2 out of 10. Cache Hit percentage is 20%

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