opp p 2.pts Which of the following may lead to a reduction in cache capacity mis
ID: 3918420 • Letter: O
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opp p
2.pts Which of the following may lead to a reduction in cache capacity misses? Mark all that apply switching from write-back to write-through. Increasing cache size increasing assoclativity (for a glven capacity) Decreasing block size (for a given capacity) 2 pts D Question 4 Which kind of dependence can cause data hazards in a single-core, pipelined, in-order processor? Mark all that apply. # read-after-write dependence 2 write-after-read dependence write-after-write dependence read-after-read dependenceExplanation / Answer
3) 1 and 3 are correct.
Reducing cache Miss Rate
1. Reduce Misses via Larger Block Size
2. Reduce Misses via Higher Associativity
3. Reducing Misses via Victim Cache
4. Reducing Misses via Pseudo-Associativity
5. Reducing Misses by HW Prefetching Instr, Data
6. Reducing Misses by SW Prefetching Data
7. Reducing Misses by Compiler Optimizations
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4) first three are answers.last one is not a data hazard.
Data Hazards
Data hazards occur when instructions that exhibit data dependence, modify data in different stages of a pipeline. Hazard cause delays in the pipeline. There are mainly three types of data hazards:
1) RAW (Read after Write) [Flow dependency]
2) WAR (Write after Read) [Anti-Data dependency]
3) WAW (Write after Write) [Output dependency]
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