2) For a direct-mapped cache design with a 32-bit address, the following bits of

Question

2) For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Complete the table for other parameters. Consider 16-bit for each word. Tag field Index field Offset field Total bits of cache Cache line size Number of Data bits of cache**(in bits) words for each block b31-b12 b11-b4 b31-b11 B10-b5 b31-b13b12-b6 b3-b0 b4-b0 b5-b0 *Total bits of cache valid bit+tag bits for each block+ block bits for data **Data bits of cache - block bits for data

Explanation / Answer

a) tag =b31-b12 = 20 bit ,index = 8 bit , offset = 4 bit

Total bit of cache = 1+20+28*24*8 = 32789

Data bit cache = 32768

Cache Line Size = 24 =16 Byte = 16*8 = 128 bit

Number of   word for each block =   block size / word size = 24*23/23 = 16 words

b)

tag =b31-b11 = 21 bit ,index = 6 bit , offset = 5 bit

Total bit of cache = 1+21+26*25*8 = 16406

Data bit cache = 16384

Cache Line Size = 25 =32 Byte = 16*8 = 256 bit

Number of   word for each block =   block size / word size = 25*23/23 = 32 words

c)

tag =b31-b13 = 19 bit ,index = 7 bit , offset = 6 bit

Total bit of cache = 1+20+27*26*8 = 65556

Data bit cache = 65536

Cache Line Size = 26 =64 Byte = 16*8 = 512 bit

Number of   word for each block =   block size / word size = 26*23/23 = 64 words

Related Questions

Navigate

• Browse (All)
• Browse 2
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.