Question 2: Assume an architecture with 32-bit addressing where memory is addres

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Question 2: Assume an architecture with 32-bit addressing where memory is addressed by byte (equivalent to MIPS). Complete the table below Direct mapped 4-way associative 8-way associative #of Line | #of Tag bits per | #of Tag bits per | #of | Tag bits per blocks sets block sets block sets block size 64 32-bit b) 256 128-bit 1 Question 3: Assume a memory hierarchy that uses primary cache that can be accessed in 1 cycle. The primary cache is backed up by the main memory. A main memory access takes 100 cycles to complete (miss penalty of the primary cache is 100 cycles). If the miss rate of the primary cache is 396, what is the average memory access time for this memory hierarchy?

Explanation / Answer

question 3)

.Effective Memory Access Time = Cache access time * hit rate + miss rate * Miss penalty
The above formula is too simple and given in many texts. But it hides what is exactly miss penalty. Because it depends on the implementation and there are simultenous cache look up and hierarchical. Unless otherwise stated in question always assume hierarchical access (case for write through cache explained below). So, for hierarchical cache, we can have the formula:
Effective Memory Access Time = Cache access time * hit rate + (1 - hit rate) * (cache access time + main memory access time)
= Cache access time + (1 - hit rate) * main memory access time

1-hit rate= miss rate

average memory access time= 1 cycle + 0.03*100 cycles = 4 cycles

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