Part I Consider a computer that you have used or now use. (You may make an assum

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Question

Part I

Consider a computer that you have used or now use. (You may make an assumption on word size if needed.)

How large is the memory of the computer?

How long is a word in the computer above?

How many bits are required to address the bytes in that memory?

How many data lines are required to read data from the computer memory?

Part II

Does your computer have cache?

If so how big is it?

How does your cache size compare with the size of main memory?

Do you know what kind of cache it is?

How did you find out about your computer's cache?

Make an assumption that your cache is either:

Fully associative

Direct mapped

Two-way set-associative

Four-way set-associative

Using the relationships in Part I above, determine:

the size of the Tag and Word for Associative cache;

the size of the Tag, Line, and Word for Direct-Mapped Cache ;

the size of Tag, Set, and Word for K-Way Set-Associative Cache.

You may make any assumptions necessary including the number of Words in each block (recommend 2 or 4 or 8)

Part III

Given the following:

Logical Memory size of 1000

Physical Memory size of 2000

Page (and frame) size of 100

Block A contains data for a program

Select Block A’s size and its starting point in both memories. Then write the page table for Block A based on your selections.

See below for the layout of both memories and an example of Block A of size 200.

Logical Memory Physical Memory

location/ page location/frame

0 to 99/ 0

100 to 199 /1 Block A

100 to 199/ 1

200 to 299/ 2 Block A

200 to 299/ 2

300 to 399/ 3

400 to 499/ 4

500 to 599/ 5

600 to 699/ 6

700 to 799/ 7

800 to 899/ 8

900 to 999/ 9

1000 to 1099/ 10

1100 to 1199/ 11

1200 to 1299/ 12

1300 to 1399/ 13 Block A

1400 to 1499/ 14 Block A

1500 to 1599/ 15

1600 to 1699/ 16

1700 to 1799/ 17

1800 to 1899/ 18

1900 to 1999/ 19

Page

Frame

Part IV

Discuss the pros and cons of paging.

0 to 99/ 0

100 to 199 /1 Block A

100 to 199/ 1

200 to 299/ 2 Block A

200 to 299/ 2

300 to 399/ 3

400 to 499/ 4

500 to 599/ 5

600 to 699/ 6

700 to 799/ 7

800 to 899/ 8

900 to 999/ 9

1000 to 1099/ 10

1100 to 1199/ 11

1200 to 1299/ 12

1300 to 1399/ 13 Block A

1400 to 1499/ 14 Block A

1500 to 1599/ 15

1600 to 1699/ 16

1700 to 1799/ 17

1800 to 1899/ 18

1900 to 1999/ 19

Explanation / Answer

component 1)

it is having 4gb of RAM
it is 32- bit working machine,x32 –based processor
c)

2^eight = 256

2^10 = 1024 = 1 KB

2^20 = 1 MB

2^30 = 1 GB

2^32 = 4,294,967,296 = four GB

due to the fact that 4 GB = 2^32, you will need 32 bits to deal with that 4 GB of reminiscence.

The most reminiscence you could address with 32 bits is 4 GB.
facts line

With laptop microchips, an information line is an electrical line or circuit that carries data and determines whether a bit represents a zero or a 1.
2. whilst relating to a cable or wire, a statistics line, is a cable that is used to transmit records communications between two exclusive factors. as an example, a smartphone cord is taken into consideration a data line.

you have got eight bits for each location, consequently, your memory desires a statistics bus with eight lines. every time you examine a region the 8 bits which can be saved at that place are loaded (through the memory chip) on the four-line information bus.

component II

sure my pc having a cache
A CPU cache is a cache used by the valuable processing unit (CPU) of a pc to lessen the average time to access data from the principle memory. The cache is a smaller, quicker memory which stores copies of the data from frequently used main reminiscence places.

Cache reminiscence degrees

Cache memory is rapid and pricey. historically, it is classified as "levels" that describe its closeness and accessibility to the microprocessor:

stage 1 (L1) cache is extremely rapid however tremendously small and is usually embedded in the processor chip (CPU).
level 2 (L2) cache is often more capacious than L1; it could be positioned at the CPU or on a separate chip or coprocessor with a high-speed alternative gadget bus interconnecting the cache to the CPU, in order no longer to be slowed by means of visitors on the main machine bus.
level three (L3) cache is usually specialized reminiscence that works to enhance the overall performance of L1 and L2. it can be drastically slower than L1 or L2, however, is generally double the velocity of RAM. within the case of multicore processors, every middle may have its own devoted L1 and L2 cache, however, proportion a commonplace L3 cache. while a guidance is referenced within the L3 cache, it's miles commonly improved to a better tier cache.
How-to test Cache size?

this can be completed with a simple windows command line device WMIC. to test, the kind the code in cmd a display within the field under. all the values returned may be KB.

wmic cpu get L2CacheSize, L2CacheSpeed, L3CacheSize, L3CacheSpeed
L2 CACHESIZE 256KB

L3 CACHESIZE 3072KB

My memory device that makes use of a 32-bit address to deal with on the byte degree, plus a cache that uses a sixty- four-byte line length.

a. assume a direct mapped cache with a tag field in the address of 20 bits. show the address layout and decide the following parameters: a variety of traces in a cache, length of the tag.

b. assume an associative cache. display the cope with a layout and determine the following parameters: a wide variety of traces in a cache, size of tag.

c. count on a four-way set-associative cache with a tag area within the cope with of 9 bits. show the deal with layout and determine the subsequent parameters: a variety of lines in the cache, length of the tag.

solution:

direct mapped cache

a. cope with layout: Tag = 20 bits; Line = 6 bits; word = 6 bits.

wide variety of traces in cache 2r = 26 = sixty four; length of tag = 20 bits.

associative cache

b. cope with format: Tag = 26 bits; word = 6 bits.

variety of traces in cache = undetermined; length of tag = 26 bits.

4-way set-associative cache

c. address layout: Tag = 9 bits; Set = 17 bits; word = 6 bits.

variety of traces in set = ok = 4; quantity of sets in cache = 2d = 217; range of traces in cache = okay × 2d =219; size of tag = 9 bits

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