Design and verify a communications interface. Often data sent over a data link a

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Design and verify a communications interface. Often data sent over a data link are organized as packets of data, each packet containing some identification bits, data, and some check bits used to determine if a transmission error has occurred. Your hardware must meet the following specification: Inputs: Clock: Reset: //reset is active low Clear: //clears output registers - active high InData[11: 0]: //Input data, organized as follows: // InDatal [11: 8] contains the?'header' // InData[7: 4] contains the 'data payload' // InData[3: 1] are not used // InData[0] is a parity bit. It is '1' if InData[7: 4] is meant to be even parity. // A new 'InData' arrives every clock Outputs: All outputs are registered and are cleared when 'reset' is low or 'clear' is high. Payload[3: 0]: // is changed to contain the?'data payload', when 'InData', is of type 1. Count[7: 0]: // total count of type 1 datas Error[7: 0]: // number of type 1 datas of wrong parity Clock 10101010101010101010101010 Clear 10000000000000000000000001 InData 1F1 0E0 171 0E0 (ie., 1F1: 'type 1', payload=F, parity should be even 0E0: 'not type 1', payload=E, odd parity 170: 'type 1', payload=7, payload should have been even parity Payload 0 FF77 The piece of hardware checks InData on each clock cycle. If InData [11: 8]=1, then it transfers the middle four bits of InData to payload and increments count. At the same time, it checks the parity of the middle four bits and sees if it is as expected. If it is not, then there is a transmission error, and error is incremented.

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2 Design and Verification of Serial Peripheral Interface M.Sandya1 , K.Rajasekhar2 1. Department of E.C.E, Akula Sree Ramulu Engineering College, Tetali 2. H.O.D, Department of E.C.E, Akula Sree Ramulu Engineering College, Tetali Abstract— The objective of this project is to design SPI Master Core using Verilog and verify the code using system verilog. Serial Peripheral Interface (SPI) is an interface that facilitates the transfer of synchronous serial data.SPI (Serial Peripheral Interface) is a synchronous serial data link that operates in full duplex mode. It communicates in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select line .Serial Peripheral Interface of symmetrical structure can be synthesized using Xilinx 12.3, and then can be simulated using Questa 10.0b. It is a popular interface used for connecting peripherals to each other and to microprocessors. The verification of the project is done using system verilog. Keywords— SPI interface; serial; Verilog HDL; system Verilog I. INTRODUCTION In our days microcontroller embedded systems are widespread in a large area of products from industrial, medical, educational to domestic domains, there are often many modules in the designs. For example, nearly every system includes: some intelligent control, usually a microcontroller core; General-purpose circuits like LCD drivers, remote I/0 ports, RAM, EEPROM, or data converters; Applicationoriented circuits for communication interfaces and/or computation intensive task. So the communication between these modules is very important, in many applications the interface is still the bottleneck of system performance .In such scenario the reuse of intellectual property (IP) macrocells is becoming the center of gravity for design productivity and the key for being able to produce chips that really work. All the integrated components must be connected each other and every SoC must be linked each other in an efficient way that allows a fast and error-free communication .The communication among SoC is the key to grant high performances: the most used solution for interconnecting SoC is a serial bus which presents great advantage in terms of costs .Using few wires to link different devices means few occupied area and consequently minor costs for the producer. A large number of serial protocols are actually used, so if a designer wants to create a SoC that can communicate using various protocols he must equip his system with a large number of interfaces, despite the fact that when the SoC is on the field usually only few of the supported protocols will be used. In this work the design and verification of SPI interface is presented. II. SPI BUS PRINCIPLE SPI is a synchronous serial bus protocol developed by Motorola and integrated in many of their microcontrollers. SPI bus consists of four signals: master out slave in (MOSI), master in slave out (MISO), serial clock (SCLK), and activelow chip select (CS). As a multi-master/slave protocol, communications between the master and selected slave use the unidirectional MISO and MOSI lines, to achieve data rates in full duplex mode. With SPI we can connect as many devices as many pins we have on the main microcontroller. The speed of the communication between ICs is much faster. Full Duplex communication is done using SPI. Figure 1.SPI Block diagram III. DESIGN PRINCIPLES V

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