You are to compare banked versus pipelined implementation of an L1 data cache. A

Question

You are to compare banked versus pipelined implementation of an L1 data cache. Assuming a 64 KB 2-way set associative cache with 64-B blocks, the pipelined cache has 3 pipe stages. A banked implementation, on the other hand, has two 32 KB 2-way set associative banks. Please use CACTI1 , assuming a 65-nm technology, to find the cycle time in comparison to the access time, and find out the number of pipe stages the cache will take up. Compare also the area and total dynamic energy per access of the pipelined design versus the banked design. Explain which takes up less area and which requires more power.

Explanation / Answer

on a read miss, wait for the write buffer to go empty•Faster scheme: Check write buffer addresses against read miss addresses,if no match, allow read miss to go ahead of writes, else, return value in writebuffer

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