1. Fig. 1 shows the architecture of a RISC computer and its instruction format.
ID: 3872557 • Letter: 1
Question
1. Fig. 1 shows the architecture of a RISC computer and its instruction format. The instrcutions are: Load (L), Store (S), Branch (B), Jump (J), Register-to-Register (R2R), and Reserved (X). Bit 25 is the literal bit. Some of typical operations are:
LDR D,(S1,S2) [D] [M([S1] + [S2])] Register indirect with double indexing
LDR D,(S1,#L) [D] [M([S1] + L)] Register indirect with literal offset
STR (S1,#L),S2 [M([S1] + L)] [S2] Register indirect with literal offset
ADD D,S1,S2 [D] [S1] + [S2] Register to register
ADD D,S1,#L [D] [S1] + L Register to register with literal operand
BEQ L [PC] [PC] + 4 + L This is a relative conditional branch
JMP (S1,#L)
Assume r1=2B0016, r2=C16, answer the following questions:
(2) 4-bit Parameters can be used to design 24 R2R instruction. Using these 4-bit parameters to design the following instructions.
AND D,S1,S2
OR D,S1,S2
XOR D,S1,S2
And show the 32-bit number for
AND r0,r1,r2
AND r0,r2,#15
Explanation / Answer
RISC Instruction: and D,S1,S2
Operation: $D=$S1 & $S2
Explanation: Logical AND of 3 integers namely S1 AND S2 IS PERFORMED AND RESULT IS STORED IN D.
2. OR D,S1,S2
RISC INSTRUCTION: or D,S1,S2
Operation: $D=$S1|$S2
Explanation: Logical OR Operation is performed on two integers namely S1 , S2 and the result is stored in D.
3. XOR D,S1,S2
RISC INSTRUCTION: xor D,S1,S2
Operation: $D=$S1 $S2
Explanation: Logical XOR Operation is performed on two integers namely S1 , S2 and the result is stored in D.
4. AND r0,r1,r2
RISC INSTRUCTION: and r0,r1,r2
Operation: $r0=$r1& $r2 ($r0=2B0016 & C16)
Explanation: Logical OR Operation is performed on two integers namely r1=2B0016 and r2=C16, and the result is stored in r0.
5. AND r0,r1,#15
RISC INSTRUCTION: and r0,r1,#15
Operation: $r0=$2B0016 & 15
Explanation: Logical OR Operation is performed on two integers namely 2B0016 , 15 and the result is stored in r0.
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