Hello. I\'m supposed to write a code in verilog to implement this ALU. The ALU s
ID: 3870634 • Letter: H
Question
Hello. I'm supposed to write a code in verilog to implement this ALU. The ALU should perform 10 functions on 8 but inputs and will generate an 8-bit result (Result), a one-but carry (C), and a one bit zero bit (Z). To show which of the 10 functions to implement the Alu_Ctrl will be used as the selection lines.Table 1: Arithmetic Logic Unit 1 Alu Ctrl Instruction Operation (Mnemonic) Loads ACCA with the value on the Data bus. Z changes to 1 if ResultO. (Load ACCA fron Data) Adds the value on the Data busto, the value in ACCA and saves the result in ACCA. C is the carry (out) from addition and Z is set if the result is 0. (Add ACCA and Data) LDDA ADDA Subtracts the value on the Data bus from the value in ACCA and saves the result in ACCA. C is the carry (in) from subtraction and Z is set if the result is 0. (Subtract value in Data from ACCA) SUBA Perforn a bitwise AND of the value on the Dat a bus with the value in ACCA. Save the result in ACCA. C should be the logical AND of th value on the Data bus with the value in ACCA. Z is set if the result is 0. (AND of ACCA and value on Data) Perform a bitwise OR of the value ou the Data Ibus with the value in ACCA. Save the result in ACCA. C should be the logical OR of the value on the Data bus with the value in ACCA. Z is set if the result is 0. (OR of ACCA and value on Data) ANDA ORAA Replace the value in ACCA with its one's complement. C is set to 1 and Z is set if the result is 0. (Compliment ACCA) Increment value in ACCA. Z is set if the result is 0. (INCA ACCA COMA (INCA LSLA Logical shift left of ACCA. C is set to the previous MSB of ACCA and Z is set if the result is 0. (Logical shift left ACCA) Logical shift right of ACCA. C is set to the previous LSB of ACCA and Z is set if the result is 0. (Logical shift right ACCA) LSRA Arithmetic shift right of ACCA. C is set to the previous LSB of ACCA and Z is set if the result is 0. (Arithmetic shift right ACCA) Zero the value of ACCA. C is set to 0 and Z is set to 1. (Zero ACCA) ASRA ZERO RST Reset ACCA to OxFF. C is set to 0 and Z is set to 0. (Reset ACCA
Explanation / Answer
module alu(a,b,cin,alu,carry,zero,Alu_ctrl); // a=ACCA, b=DATA+OUT, Z=zero, c=Carry
input [7:0] a,b; // port A,B
input cin ; // carry input from carry flag register
output [7:0] alu; // the result
output carry; // carry output
output zero ; // zero output
input [3:0] Alu_ctrl ; // functionality control for ALU
wire [8:0] result; // ALU result
assign result = alu_out(a,b,cin,Alu_ctrl);
assign alu = result[7:0];
assign carry = result[8] ;
assign zero = z_flag(result) ;
function [8:0] alu_out;
input [7:0] a,b ;
input cin ;
input [3:0] Alu_ctrl ;
case ( Alu_ctrl )
4'b0000: alu_out=a; // load port A
4'b0001: alu_out=a+b ; // ADD
4'b0010: alu_out=a-b ; // decrement data on port B
4'b0011: alu_out=a&b ; //bitwise AND
4'b0100: alu_out=a|b; // bitwise OR
4'b0101: alu_out=a+8'b00000001 ; // 1s complement
4'b0110: alu_out=a+8'b00000001 ; // increment data on port A
4'b0111: alu_out={b[7:0],1'b0}; // Shift Left
4'b1000: alu_out={b[0],1'b0,b[7:1]}; // Shift Right
4'b1001: alu_out={a[7:0],cin}; // Rotate Left
4'b1010: alu_out={a[0],cin,a[7:1]}; // Rotate Right
4'b1011: alu_out=8'b00000000; // zero Acc
default : begin
alu_out=9'bxxxxxxxxx;
$display("Illegal CTL detected!!");
end
endcase /* {...,...,...} is for the concatenation.
{ADD_WITH_CARRY,SUB_WITH_BORROW}==2'b11 is used
to force the CARRY==1 for the increment operation */
endfunction // end of function "result"
function z_flag ;
input [8:0] a8 ;
begin
z_flag = ^(a8[0]|a8[1]|a8[2]|a8[3]|a8[4]|a8[5]|a8[6]|a8[7]) ; // zero flag check for a8
end
endfunction
endmodule
//test_bench is not provided as initial conditions are not given. Code the test_bench and run the code... Thank You
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