1) Manually generate the truth table for even parity function (P) for a 2-bit me
ID: 3870588 • Letter: 1
Question
1) Manually generate the truth table for even parity function (P) for a 2-bit message (x, y). Manually derive the algebraic expression for the Boolean function P. Manually minimize the Boolean function for P (i.e. use either a Karnaugh map or Boolean algebra) and generate the minimal AND-OR realization.
2) Use WinLogiLab to derive both the minimal AND-OR and the equivalent minimal all-NAND gate realizations for P (see Figures A-1 and A-2 in the Appendix for a solved example that uses 3 message bits). Capture both the AND-OR and all-NAND logical schematics into a file and hardcopy. (As a side note, when it comes to physical construction or realization of the logic circuit, it is much easier to locate multi-input NAND gate ICs than multi-input AND gate ICs due to manufacturability of the former.)
3) Draw the physical circuit diagram of the all-NAND realization specifying the pin numbers of all the gates using the WinLogiLab WireDiagm utility. You should be utilizing 7400 quad 2-input NAND ICs along with 7404 NOT gates for complementation. Save the circuit diagram to a file and print a hard copy.
4) Repeat above steps for the parity checker function called (C), which checks an incoming 3-bit message (i.e. 2 bits for original message and 1 bit for the parity) for even parity (see Figures A-3 and A-4 for a solved example using a 4-bit message with 3 original message bits and 1 parity bit). The circuit output should be 1 if the message is not valid (i.e. the 3-bit binary message with 1 bit representing the parity information has odd parity). You should be utilizing 7410 triple 3-input NAND and 7420 dual 4-input NAND ICs along with 7404 NOT gates for complementation.
5) Connect the parity generator and parity checker circuits as shown in Figure 1 to form an end-to-end system. Using the WinLogiLab DigitalSim utility, simulate your design to validate their functionality. Capture the simulation circuit schematics and the simulation session to a file and hardcopy.
6) Devise an experiment set up to drive the inputs of interfaced parity generator/checker circuitry using the data switches (SW0 through SW7) on the ETS-7000. Utilize the LED displays on the ETS-7000 for observing the outputs of interest. Draw the physical schematics (i.e. all ICs with their pin layout and numbering along with all wiring shown) using the WinLogiLab WireDiagm utility.
Parity Tranmission medium Parity C induc Figure 1. Parity Generation and CheckExplanation / Answer
Part-(1)
A parity generator is a combinational logic circuit that generates the parity bit in the transmitter.
The sum of the message bits and parity bits can be even or odd . In even parity, add 1 to parity bit if number of 1’s are odd in message bits.
Even parity bit generator (P) with two bit message (x,y):
Truth table:
2 bit message
Even parity bit generator (P)
0
0
0
0
1
1
1
0
1
1
1
1
K-map simplification:
Minimal AND-OR realization:
2 bit message
Even parity bit generator (P)
0
0
0
0
1
1
1
0
1
1
1
1
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