A CPU has a logical address format with 3 bits for page number and 2 bits for pa

Question

A CPU has a logical address format with 3 bits for page number and 2 bits for page offset. The page table for a process is:

0. 6

1. 9

2. 8

3. 0

4. 3

5. 1

6. 4

7. 7

Map the following logical addresses to the physical address -- frame_number.offset and the corresponding byte address. (The dot separates the page number from the offset. All numbers are in base 10. )

a=3.2, b=0.3, c=7.1

a: 0.2 = 2

b: 6.4 = 27

c: 7.1 = 28

a: 0.2 = 2

b: 6.3 = 27

c: 7.1 = 29

a: 3.2 = 14

b: 6.3 = 27

c: 7.1 = 29

a: 0.2 = 2

b: 3.3 = 15

c: 7.1 = 26

a: 0.2 = 2

b: 6.4 = 27

c: 7.1 = 28

Explanation / Answer

The logical addresses:
a= 3.2 , b= 0.3, c=7.1
is mapped to following physical addresses as per the page tabel and the corresponding byte numbers are .
Every page has 4 bytes as the page offset is 2 bytes. So the byte number will be page number * 4 + the page offset (i.e digit after . in the logical address)
a= 0.2 , 2     (physical page for 3rd virtual page is 0 as per the page table. )
b= 6.3 ,27     (physical page for 0th virtual page is 6 as per the page table)
c = 7.1 , 29   (physical page for 7th virtual page is 7 as per the page table)

Related Questions

Navigate

• Browse (All)
• Browse A
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.