a) Suppose a CPU with a write-through write-allocate cache achieves a CPI of 2.
ID: 3866044 • Letter: A
Question
a) Suppose a CPU with a write-through write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache? (Assume each miss generates a request for one block.)
b) For a write-back, write allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2?
Data Reads per 1000 instructions Data Writes per 1000 instructions Instruction Cahce Miss Rate Data Cache Miss Rate Block size (Bytes) 250 100 0.30% 2% 64Explanation / Answer
I = number of instructions executed by the program.
The number of cycles for reading a block from the main memory will be 64/W where W is the read/write band-width.
1) The data cache read miss penalty (cycles) = I × 250/1000 × 0.02 × (64/W + 1).
The data cache write miss penalty (cycles) = I × 100/1000 × 0.02 × (64/W + 1)
The instruction cache read miss penalty = I × 0.003 × (64/W + 1)
In order that CPI 2, one has Hit time + miss penalty = I + I × [0.25 × 0.02 + 0.1 ×0.02 + 0.003] × (64/W + 1) I × 2. hence W 64/99 ~ 0.646 Byte/cycle.
2) data cache read miss penalty = I × 0.25 × 0.02 × (1 + 0.3) × (64/W + 1)
Data cache write miss penalty = I × 0.1 × 0.02 × (1 + 0.3) × (64/W + 1)
read miss penalty = I × 0.003 × (64/ W + 1)
Total execution time = hit time + miss penalty = I + I × [0.25 × 0.02 × 1.3 + 0.1 × 0.02× 1.3 + 0.003] × (64/W + 1) 2I. therefore 0.0121 × (64/W + 1) 1. Hence W 0.784 Byte/cycle.
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