1. (22 pts) Circle the selected answer for T/F and multiple-choice questions; an

Question

1. (22 pts) Circle the selected answer for T/F and multiple-choice questions; and fill in the blanks for
the rest. Each part is 2 points.

a) T / F A processor can have different CPIs for different programs.
b) T / F In multi-cycle implementation the first two stages, instruction fetch and
instruction decode, are the same for all instruction classes.
c) T / F Increasing the depth of pipelining always decreases performance.
d) T / F Pipelining improves the performance by increasing throughput.
e) T / F To pass data from an early pipeline stage to a later pipeline stage, the data must be
placed in a pipeline register not to lose the data when the next instruction enters
that pipeline stage.
f) T / F Data forwarding resolves the data hazard that occurs when an instruction tries to
read a register following a load instruction that writes the same register.
g) The ideal speedup of a pipelined system with four ideal stages is _______________________.
h) One solution to data hazards can be ________________________________________________.
i) One solution to structural hazards can be ____________________________________________.

j) Which one of the following processors has the highest possible MIPS rate in ideal
conditions?
a. A single-issue processor driven by a 1 GHz clock.
b. A 2-issue processor driven by a 500 MHz clock.
c. A 4-issue processor driven by a 250 MHz clock.
d. An 8-issue VLIW processor driven by a 200 MHz clock.

k) Which one of the following is NOT calculated by the ALU?
a. Arithmetic result for arithmetic instructions
b. Memory address for load/store instructions
c. Branch target address
d. Address of the next instruction

Explanation / Answer

1.TRUE.

A processor can have different CPI s for different program

2.TRUE

In multicycle implementation the first two stages will be same for all instruction set.

3.FALSE

Increase in Pipeling depth increases the performance and never decreases the performance

4. TRUE

Pipelining increases the performance by increasing the throughput

5.TRUE

To pass data from one stage to another the data must be stored in the register to prevent the data loss

6;TRUE
This is a datahazard called Read after write

Here a register must be read and it should be read only after the write operation, But if it happens before then the data hazard occurs,

7.Ideal speed up is equal to the number of stages in the pipeline,

8.Solution to data hazard is data or register forwarding

9.Resource Rep;ication is one of the solution to the structural hazard

10.Single issue processor has highest MIPS rate

11.Address of the next instruction is calculated using AGU and not ALU

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