Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

i need the currect answers Superscalar architectutre. u v simple x U Fetch x Exe

ID: 3856601 • Letter: I

Question

i need the currect answers

Superscalar architectutre.
u
v
simple x
U
Fetch x
Executes x
12.2 tps x

i have these in the above but the only currect answers are

1-Superscalar architectutre.
2-u
3-v

4-simple x im not sure about this

5-U

10. The Pentium processor used a architecture, w hich implies that it has two pipelines. The first pipeline, can handle any instruction. The second pipeline, can only handle The first pipeline, known as the e any instruction. The second pipeline, known as de cond pi Floating point instructions are first placed in the eventually are placed in the floating point unit; instructions. pipeline, where they ating point unit; an exception to this rule is that the instructio n can stay in the u pipeline since it involves only e instruction's execution. Using this type of architecture with two pipelines (how many?) the operands, i.e. no floating-point operations are taking place during the instruction's exe Pentium can achieve a maximum throughput of instructions per clock. cution. Using this type of architecture with two pipelines, the one else wro

Explanation / Answer

The correct answers are

The Pentium processor used a Superscalar architecture, which implies that it has two pipelines.The first pipeline, known as u pipeline, can handle any instruction.The second pipeline, known as the v pipeline, can only handle simple instructions.Floating point instructions are first placed in the U pipeline, where they eventually are placed in the floating point unit; an exception to this rule is that the fetch instruction can stay in the u pipeline since it involves only executes the operands, ie. no floating-point operations are taking place during the instruction's execution.Using this type of architecture with two pipeline Pentium can achieve a maximum throughput of 12.2 tps instructions per clock.