Project Summary: Scenario: In this project, you are asked to design the main cor
ID: 3855535 • Letter: P
Question
Project Summary: Scenario: In this project, you are asked to design the main core of a digital watch. This watch is capable to print out time; second, minute, hour and, date; year, month and day. It is also able to save many alarms and rearrange them by priority (closet first). In addition, the user has to have the ability to set time and dates. Full Description: For this project, you need to design and to implement in FPGA a core of digital watch. This circuit takes the 50MHZ clock signal and generate time signal through three output buss 7 wires each in order to drive 7 segments I LEDS For date, use the same 7 segments to show them by numbers like: July 12h 2017 the LEDs will print: 12 07 2017. The eight 7 segments LEDs available in the Altera terasic DE2-115 board are sufficient for these tasks This watch will have many operations modes; 1. Mode A: normal operating mode for time, time is showing on the L.EDs 2. Mode B: normal operating mode for date, date is showing on the LEDs. 3. Mode C: setup mode for time 4. Mode D: setup mode for date. 5. Mode E: setup mode for alarm. 6. Mode F: Alarm operating. You will use some switches of these board in order to switch from mode to another, keep in mind, these switches need soft debouncer program to be implemented. We strongly recommend you to search for this keywords and modules: 1. Binary counter 2. Modulo counterExplanation / Answer
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.clock_div.all;
entity digital_clock is
port (
clk: in std_logic;
rst_n: in std_logic;
H_in1: in std_logic_vector(1 downto 0);
H_in0: in std_logic_vector(3 downto 0);
M_in1: in std_logic_vector(3 downto 0);
M_in0: in std_logic_vector(3 downto 0);
H_out1: out std_logic_vector(6 downto 0);
H_out0: out std_logic_vector(6 downto 0);
M_out1: out std_logic_vector(6 downto 0);
M_out0: out std_logic_vector(6 downto 0)
);
end digital_clock:
port (Bin: in std_logic_vector(3 downto 0);Hout: out std_logic_vector(6 downto 0));
end component;
signal clk_1s: std_logic; -- 1-s clock
signal counter_hour, counter_minute, counter_second: integer;
signal H_out1_bin: std_logic_vector(3 downto 0);
signal H_out0_bin: std_logic_vector(3 downto 0);
signal M_out1_bin: std_logic_vector(3 downto 0);
signal M_out0_bin: std_logic_vector(3 downto 0);
begin
process(clk_1s,rst_n) begin
if(rst_n = '0') then
counter_hour <= to_integer(unsigned(H_in1))*10 + to_integer(unsigned(H_in0));
counter_minute <= to_integer(unsigned(M_in1))*10 + to_integer(unsigned(M_in0));
counter_second <= 0;
elsif(rising_edge(clk_1s)) then
counter_second <= counter_second + 1;
if(counter_second >=59) then -- second > 59 then minute increases
counter_minute <= counter_minute + 1;
counter_second <= 0;
if(counter_minute >=59) then -- minute > 59 then hour increases
counter_minute <= 0;
counter_hour <= counter_hour + 1;
if(counter_hour >= 24) then -- hour > 24 then set hour to 0
counter_hour <= 0;
end if;
end if;
end if;
end if;
end process;
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