Wrtite Write a module (or modules) to demoostrate blocking and non-blocking assi
ID: 3852858 • Letter: W
Question
Wrtite Write a module (or modules) to demoostrate blocking and non-blocking assignments in always blocks. suggestion - to make things easy to demonstrate, use a slow clock trigger your always blocks in order to able to see LEDs updating when you expect them to. Switches and LEDs are probably the easiest way to go with this.
So I had a code but it needs to be modified like above. This is the code:
module blocking;
reg x, y, z;
initial begin
x = #10 1'b1; // Execution at t=10
y = #20 1'b0; // Execution at t=30
z = #40 1'b1; // Execution at t=70
end
module blocking (clock, x, z);
input clock;
input x;
output z;
wire clock;
wire x;
reg z;
reg y;
always @ (posedge clock )
begin
y = x;
z = y;
end
module non blocking;
reg x, y, z;
initial begin
x <= #10 1'b1; // Execution at t=10
y <= #20 1'b0; // Execution at t=20
z <= #40 1'b1; // Execution at t=40
end
module non-blocking (clock, x, z);
input clock;
input x;
output z;
wire clock;
wire x;
reg z;
reg y;
always @ (posedge clock )
begin
y <= x;
z <= y;
end
endmodule
Explanation / Answer
Solution :-
The program has to run in two parts, both parts iincluding modified program is shown below:-
module complexDivider(fstclock, slwClock)
input fstclock; //clock type fast
output slwClock; //clock type slow
reg[26:0] counter;
initial
begin
counter = 0;
end
always @ (posedge fstclock)
begin if(counter == 30000000)
begin counter <= 1;
slwClk <= ~slowClock;
end
else begin
counter <= counter + 1;
end
end
endmodule.
2)
module blocking;
reg x, y, z;
initial begin
x = #10 1'b1; // Execution at t=5
y = #20 1'b0; // Execution at t=10
z = #30 1'b1; // Execution at t=15
end
module blocking (clock, x, z);
input clock;
input x;
output z;
wire clock;
wire x;
reg z;
reg y;
always @ (posedge clock )
begin
y = x;
z = y;
end
module non blocking;
reg x, y, z;
initial begin
x <= #10 1'b1; // Execution at t=5
y <= #20 1'b0; // Execution at t=10
z <= #30 1'b1; // Execution at t=15
end
module non-blocking (clock, x, z);
input clock;
input x;
output z;
wire clock;
wire x;
reg z;
reg y;
always @ (posedge clock )
begin
y <= x;
z <= y;
end
endmodule
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