use Verilog (3) Build a dual stop watch. One instance of the stop watch(2) count

Question

use Verilog

(3) Build a dual stop watch. One instance of the stop watch(2) counts up indicating the total time it has been running and the other instance indicating time left. This will require two instances of the stop watch in (2). When the second instance, which counts down from some starting value. When instance gets to 00:00 an alarm should be triggered displaying the word “Alarm” to the screen, this should also trigger make the output Alarm=1.

a. Turn in your code that meets each of these characteristics

Build a test bench for the code in (3), and set the initial time to 10 minutes and 30 seconds. Log this information into a csv file showing the count down by the second. There should be a header containing the variable names. The other stop watch instance should count up at the same time. It should also be written to the same log file in adjacent columns.

a. Turn in the test bench code,

b. log file and

c. waveforms demonstrating this behavior.

d. You should run it till the alarm is triggered so that you can show that.

USE VERILOG

Explanation / Answer

module stopwatch(
input clock,
input reset,
input start,
output a, b, c, d, e, f, g, dp,
output [3:0] an
);

reg [3:0] reg_d0, reg_d1, reg_d2, reg_d3;
reg [22:0] ticker;
wire click;

always @ (posedge clock or posedge reset)
begin
if(reset)

ticker <= 0;

else if(ticker == 5000000)
ticker <= 0;
else if(start)
ticker <= ticker + 1;
end

assign click = ((ticker == 5000000)?1'b1:1'b0);

always @ (posedge clock or posedge reset)
begin
if (reset)
begin
reg_d0 <= 0;
reg_d1 <= 0;
reg_d2 <= 0;
reg_d3 <= 0;
end

else if (click)
begin
if(reg_d0 == 9)
begin   
reg_d0 <= 0;

if (reg_d1 == 9)
begin   
reg_d1 <= 0;
if (reg_d2 == 5)
begin
reg_d2 <= 0;
if(reg_d3 == 9)
reg_d3 <= 0;
else
reg_d3 <= reg_d3 + 1;
end
else
reg_d2 <= reg_d2 + 1;
end

else
reg_d1 <= reg_d1 + 1;
end
  
else
reg_d0 <= reg_d0 + 1;
end
end


localparam N = 18;

reg [N-1:0]count;

always @ (posedge clock or posedge reset)
begin
if (reset)
count <= 0;
else
count <= count + 1;
end

reg [6:0]sseg;
reg [3:0]an_temp;
reg reg_dp;
always @ (*)
begin
case(count[N-1:N-2])
  
2'b00 :
begin
sseg = reg_d0;
an_temp = 4'b1110;
reg_dp = 1'b1;
end
  
2'b01:
begin
sseg = reg_d1;
an_temp = 4'b1101;
reg_dp = 1'b0;
end
  
2'b10:
begin
sseg = reg_d2;
an_temp = 4'b1011;
reg_dp = 1'b1;
end

2'b11:
begin
sseg = reg_d3;
an_temp = 4'b0111;
reg_dp = 1'b0;
end
endcase
end
assign an = an_temp;

reg [6:0] sseg_temp;
always @ (*)
begin
case(sseg)
4'd0 : sseg_temp = 7'b1000000;
4'd1 : sseg_temp = 7'b1111001;
4'd2 : sseg_temp = 7'b0100100;
4'd3 : sseg_temp = 7'b0110000;
4'd4 : sseg_temp = 7'b0011001;
4'd5 : sseg_temp = 7'b0010010;
4'd6 : sseg_temp = 7'b0000010;
4'd7 : sseg_temp = 7'b1111000;
4'd8 : sseg_temp = 7'b0000000;
4'd9 : sseg_temp = 7'b0010000;
default : sseg_temp = 7'b0111111; //dash
endcase
end
assign {g, f, e, d, c, b, a} = sseg_temp;
assign dp = reg_dp;


endmodule

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