You have been assigned to design a 8M x 32 bit memory board. You may use only 25

Question

You have been assigned to design a 8M x 32 bit memory board. You may use only 256K x 8 bit RAM chips with full parallel addressing. a. How many bits are required in the Address Bus (i.e. MAR) of the whole board? b. How many address pins are required per chip? c. How many data pins are required per chip? d. How many of the system address lines must be split-off and decoded for input into Chip-Enable pins. e. Consider the physical memory address X = 724288. In the memory matrix design, which row would contain this address? (Note that you need to provide the row number and the rows start from 0. As an example, if an address is on the fifth row, the row number is 4). Please answer it fully especially E.

Explanation / Answer

8M x 32--->8M address(i/p) lines and 32 data lines(o/p)

256k x 8--->256k address(i/p) lines and 8 data lines(o/p)

8M/256K =32 --> 32 rows of chips

32bit/8bit= 4   --> 4 columns of chips (i.e. 4 chips per row)(8 datalines per chip and we have 4 such chips per row so totally 8x4=32 data lines per row)

decoder used 5 X32 (as we need 32 sets (rows) of 4set(column) chips we need a 32 as output of decoder to select any of those 32rows containing 4 coloum chips we need 5X32decoder)

chips of each row will be accessed parallely that is 4 chips of a row are accessed at once.and rows are selected using the decoder.

a) How many bits are required in the Address Bus of the whole board?

8M=2^23 so we need 23 bits

b) How many address pins are required per chip?

256K = 2^18 so we need 18 bits

c) How many I/O pins are required per chip?

18 input (address lines) , 8 output(data lines) , 1 Chip-Enable pin form decoder.

d) How many of the system address lines must be split-off and decoded for input into Chip-Enable pins?

5 address lines (as we are using 5X32 decoder.)

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