3. The processor for which you are designing your application as L1i and L1d vir

Question

3. The processor for which you are designing your application as L1i and L1d virtual caches.

a. What type of data does each cache hold? [2 points]

b. Describe in detail the activities of the cache + memory system when executing the instruction [3 points] LOAD virtual address, register

c. Assume that the above instruction is executed many times in a loop, and that the instruction itself is in the cache. Also assume that memory access costs µs, and cache access costs /15 µs. What cache hit rate for “virtual address” is required for the memory system to run 5 times faster than with no caching at all? Show your work. [7 points]

d. Suppose we have a memory system that has a main memory, a single-level cache, and demand paging virtual memory. The three levels of the memory system have the following access times:

Cache 2ns Main memory

100ns

Paging disk 10ms

i. The cache has a 95% hit rate. What is the effective memory access time if we consider only the cache and main memory and ignore page faults and disk access times? [3 points]

ii. Now recalculate the effective memory access time assuming the same cache hit rate (95%) plus a page fault rate of 0.001% (i.e., 99.999% of the memory accesses succeed without producing a page fault). [5 points]

Explanation / Answer

processor has L1 chache

L1 caches are two types L1 i and L1 d caches .L1 i means instruction cache.L1 d means data cache.

instruction cache is used to speed up instruction fetch and data cache is used speed up operand fetch

instruction cache and data cache have little difference.

Instruction cache , instructions will be fetched from memory.but in data cache data will be fetched from memory and some times we have to write back.

a) instruction cache holds recently executed instructions only.

data cache holds operands and it allows to store instructions to a quite moment,in excution wise.

b)while executing load virtual adress ,register first cpu has to etch the instruction, so it searches for the instruction in instruction memory,it finds it will fetch or else it will go to main memory for fetching instruction.

in second step instruction decoder will decode the instruction. and cpu will fetch the operands from data cache.it operands are not available in data cache ,it will go to main memory for fetching.

after that instruction will be executed by cpu.later address will be stored in register.

c)here we have total 2 memory access .beacuse 1 for instruction fetch and 1 for operand fetch.
each memory access will take t micro seconds.
two memory acesses it will take 2t micro seconds.
if no caching(for both instruction cache and data cache)1/3 at all it will take 2t s.

if caching is there for both instruction and data
then every time instruction is availabel in instruction cache.
but data cache is hit rate we have to be known.
total time if operand is available in data cache then 2t/15.
if not available in data cache it has to go main memory then t+t/15=16t/15
average access time for caching is h*tc+(1-h)M
h=hit rate
tc=time to access cache
1-h =mis rate
M=mis penalty

mis penalty means memory access time t.
we have clue about averge acess time
t/15+ x=1/5 * 2t
   x= 1/3 t.

   now we will calculate average access time for data cache.
   t/3-t/15=4t /15
   now we will calculate hit rate of data cache
   4t/15=t/15 *h+ (1-h)*t then h=0.78

   hit rate of data cache will be 78% if we do calculation.

d) i. efective memory access time is hit rate*cache access time+ miss rate* main memory access time

0.95*2+0.05*100=6.9 ns

ii)

here first we can calculate avereage access time for main memory first

EAT=100ns+0.001*10*10^6 (formula mainmemory access time + page fault rate* page fault service time)

after calculation 10.1 micro seconds is the effective memory access,

now we calculate average access time for entire system is

0.95*2+0.05*10100=506.9 ns

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