Multilevel caching is an important technique to overcome the limited amount of s
ID: 3838560 • Letter: M
Question
Multilevel caching is an important technique to overcome the limited amount of space that a first level cache can provide while still maintaining its speed. Consider a processor with the following parameters: Calculate the CPI for the processor in the table using: 1) only a first level cache, 2) a second level direct-mapped cache, and 3) a second level eight-was set associative cache. How do these numbers change if main memory access time is doubled? If it is cut in half? It is possible to have an even greater cache hierarchy than two levels. Given the processor above with a second level, direct-mapped cache, a designer wants to add a third level cache that takes 50 cycles to access and will reduce the global miss rate to 1.3%. Would this provide better performance? In general, what are the advantages and disadvantages of adding a third level cache?Explanation / Answer
5.7.4: Answer
Given:
Base CPI = 1.5
Processor Speed = 2 GHZ
Main Memory Access Time = 100ns
L1 miss rate per instruction = 7%
L2 direct mapped access = 12 cycles
Global miss rate with L2 direct mapped = 3.5%
L2 8-way set associative access = 28 cycles
Global miss rate with L2 8-way set associative access = 1.5%
Miss penalty = 100ns/(1/2GHz) = 200 cycles
1) Only a L1 cache in the system:
First-level Cache CPI = 1.5 + (0.07 * 200) = 15.5
2) L2 direct-mapped cache:
L1 miss, L2 hit penalty = 12 cycles
Both miss penalty = 12 + 200 = 212 cycles
Total CPI = 1.5 + (0.07 * 12) + (0.035 * 212) = 9.76
3) L2 eight-way set associative cache
L1 miss, L2 hit penalty = 28 cycles
Both miss penalty = 28 + 200 = 228 cycles
Total CPI = 1.5 + (0.07 * 28) + (0.015 * 228) = 6.88
if Main memory access time is doubled:
Miss penalty = 2*100ns/(1/2GHz) = 400 cycles
1) Only a L1 cache in the system
First-level Cache CPI = 1.5 + (0.07 * 400) = 29.5
2) L2 direct-mapped cache
L1 miss, L2 hit penalty = 12 cycles
Both miss penalty = 12 + 400 = 412 cycles
Total CPI = 1.5 + (0.07 * 12) + (0.035 * 412) = 16.76
3) L2 eight-way set associative cache
L1 miss, L2 hit penalty = 28 cycles
Both miss penalty = 28 + 400 = 428 cycles
Total CPI = 1.5 + (0.07 * 28) + (0.015 * 428) = 9.88
If Main memory access time is cut to half:
Miss penalty = 1/2*100ns/(1/2GHz) = 100 cycles
1) Only a L1 cache in the system
First-level Cache CPI = 1.5 + (0.07 * 100) = 8.5
2) L2 direct-mapped cache
L1 miss, L2 hit penalty = 12 cycles
Both miss penalty = 12 + 100 = 112 cycles
Total CPI = 1.5 + (0.07 * 12) + (0.035 * 112) = 6.26
3) L2 eight-way set associative cache
L1 miss, L2 hit penalty = 28 cycles
Both miss penalty = 28 + 100 = 128 cycles
Total CPI = 1.5 + (0.07 * 28) + (0.015 * 128) = 5.38
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