For this problem, we will examine the performance of the TLB only, so ignore cac

Question

For this problem, we will examine the performance of the TLB only, so ignore cache accesses. Our system has the following properties: 16-bit virtual addresses Page size of 256 bytes 8-entry fully associative TLB Assuming that the TLB has just been flushed (all entries set to invalid), answer the following questions for data accesses in the following code only (i.e. ignore instruction fetches). #define ARRAY_SIZE 512 #define LEAP 4 int i; long nums[ARRAY_SIZE];//&nums; = 0 times 0100 (virtual addr) for (i = 0; i

Explanation / Answer

16bit virtual address page: 256bytes 8 fully associative TLB sizeof(long) = 4bytes Array_size = 512 elemets a. number of elements in a page = 256/4 = 64 b. Starting address in hex = 0000 0001 0000 0000 Since page size is 256bytes, page offset = 8bits (log2 256) Therefore last 8bits of starting address of array is 0000 0000 Therefore offset is 0x00 c. 64 elements are present in 1 page therefore 512 elements are present in 1/64*512 = 8 pages d. Difference in address in each loop is 4*4 (LEAP * sizeof(long)) = 16 e. number of data access: 1. Read i 2. Read base address of Num 3. Read Num[i] 4. Writeback Num[i] 5. Writeback i (after i = i+1) therefore minimum of 5 data access required f. The TLB stores the recent translations of virtual memory to physical memory and can be called an address-translation cache. During translation the page offset does not require transation, since offset in the virtual aaddress and physical address remains unchanged. So TLB stores only the Page number part. Since TLB can store the complete array(8 page long) the problem becomes much easier for loop executes 512/4 or 128 times out of 128, we will have 8 compulsary misses (When the page is encountered for the first time) therefore miss rate is 8/128 or 0.0625

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