Virtual memory uses a page table to track the mapping of virtual addresses to ph

Question

Virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. To speed up this translation, modern processors implement a cache of the most recently used translations, called the translation -lookaside buffer TLB). The following list is a stream of virtual addresses as seen on a system. Assume 4-KiB pages and a four-entry fully associative TLB with LRU replacement policy. If pages must be brought in from disk, give them the next largest unused page number. That is, the page coming in from disk (a page fault) will go to the next page in physical memory. At the start of this scenario, the largest page in memory is 12, so that page fault would go to page 13 With a 4-KiB page, the lower 12 bits of the virtual address are just the offset within the page, and can be ignored. Assume that this is a 32 bit OS. The sequence of memory addresses is: 0x0FFF 0x7A28 0x3DAD 0x3A98 0x1C19 0x1000 0x22DO

Explanation / Answer

Solution :

TLB :

22D0

not in mm

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Page table :

If you have any doubts, you can ask in comment section.

0FFF M already in mm 7A28 H cache 3DAD H cache 3A98 H cache 1C19 PF not in mm 1000 H in cache

22D0

PF

not in mm

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