There is a memory system with L1 cache and main memory. The L1 cache latency is

Question

There is a memory system with L1 cache and main memory. The L1 cache latency is 10 cycles, main memory latency is 100 cycles and L1 hit rate is 95%. Assume the latency of servicing an L1 miss is equal to the latency of the main memory. Answer the following questions. What is the total time to execute a program with X memory accesses without a cache? What is the total time to execute a program with X memory accesses with a cache? What is the speedup with the cache? If you increase the hit rate to 99%, what is the speedup with a cache?

Explanation / Answer

a) X*100 cycles it will take

b) (0.95*X*10 + 0.05*X*100)cycles

c) speedup = 100/(9.5+5) = 100/14.5

d) speedup = 100/(9.9+1) = 100/10.9

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