Problem 2: Design of a 4-bit Magnitude Comparator Design, simulate and verify a

Question

Problem 2: Design of a 4-bit Magnitude Comparator

Design, simulate and verify a 4-bit magnitude comparator in Verilog. Use a variety of inputs to test your design and include the results in your report. You may approach this problem in a hierarchical fashion. If you do so, first design a single-bit comparator and then wire four copies of the same comparator appropriately to produce a 4-bit comparator. A single bit comparator circuit has two data inputs, three control inputs and three compare outputs. The three control inputs provide a mechanism for generation of multi-bit comparators by cascading several 1-bit comparators. This is how the single bit comparator logic works. The A>B output is 1 if "the A input is greater than the B input (AB is 10)" or if "A is equal to B and the > input is 1." The A=B output is 1 if "A is equal to B and the = input is 1." The A < B output is the opposite of the A>B output. This line becomes 1 if "A input is less than B output (AB is 01)" or if "A is equal to B and the < input is 1." Based on this functional description of the 1-bit comparator, Karnaugh maps for its three outputs can be extracted easily. Since the logic is simple, you really don't need to refer to any literature other than the Verilog manual for its implementation. However, if you need any help, you could look at any elementary books on Logic Design. If you have any difficulty in understanding this problem, you may first consider a few simple numbers and make comparisons starting at the lsb moving toward the msb. If you like to take a "flat design" approach instead of the hierarchical design paradigm (that is, consider the 4-bit comparator as a single module), such a solution is also acceptable. But in practice, you generally follow a modular/hierarchical design approach.

Explanation / Answer

1. Introduction
A comparator is an important arithmetic component in a digital circuit. This is because sorting (done by a comparator) is one of the most important problems in computer engineering/science (Geetanji et al., 2011). In communication and computing systems, many important processes require the sorting of data in the areas of multiprocessing and parallel computing (Geetanji et al., 2011).
Another application of the magnitude comparator is in the vending machine, in which a magnitude comparator is used to determine if the correct coin is inserted to make for the dispensing of the correct item (Tinder, 2000). The comparison of two numbers in digital systems is an arithmetic operation used to determine if one number is greater than, equal to or less than the other number (Anjuli and Satyajit, 2013). The magnitude comparator used for this purpose is a combinational circuit which compares two numbers, A and B, and determines their relative magnitude.
The magnitude comparator comes in the form of an Integrated Circuit (IC) form. The IC can be based on TTL (Transistor Transistor Logic) technology or it can be based on CMOS (Complementary Metal Oxide Semiconductor) technology (Fairchild Semiconductor, 1999).
It is the objective of this study to use Simulink to design the 4-bit magnitude comparator; which is a far better way of achieving the design than traditional methods like schematic capture. This is because Simulink allows us to focus on the modelling directly.
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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2. Methodology
2.1 The 4-Bit magnitude comparator
The block diagram of the circuit for comparing two n-bit numbers is shown in Figure 1 below:
The circuit compares two n-bit binary numbers A and B, and gives three outputs:
GT (A > B), EQ (A = B), and LT (A < B)
To compare two numbers, the circuit must have 2n inputs and 22n entries in the truth table (Anjuli and Satyajit, 2013). Thus, for 4-bit comparator, the inputs will be 2x4 = 8 inputs and the entries in the truth table will be 22x4 = 28 = 256. Due to space constraint, only a section of the entries of the truth table is presented below:
As can be seen in Table 1, the 4-bit comparator compares the two numbers, each having 4-bits (A3 to A0 and B3 to B0).
Figure 1: An n-bit magnitude comparator block
Table 1: Truth table for 4-bit comparator
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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2.2 The 4-Bit magnitude comparator design equations
The Boolean expressions (Anil, 2007) representing the conditions shown in the truth table (Table 1) are:
where X, Y, and Z are the three variables which represent the conditions A=B, A>B, and A<B respectively. Equation 1 is explained by Table 2 below:
ANDing x3, x2, x1, and x0 ensures X produces a ‘1’ when x3, x2, x1, and x0 are all in the logic ‘1’ state.
The variable Y in equation 2 will be ‘1’ if A>B during the comparison operation. Along the same line, if A<B, the variable Z will be ‘1’. As an example if we have the data shown in Table 3 below:
It can be seen that at A>B, because A1>B1. Hence substituting this into equation 2 at
stage of the computation results in ‘1’, hence Y=1 because the operation of an OR gate is being performed and when one of the inputs is ‘1’, the output of the gate is ‘1’ irrespective of what the other inputs may be.
2.3 Simulink environment
The Simulink environment makes it possible to design and develop different types of engineering models, from simple models to advances models, as long as such models can be characterized by equations. In the Simulink environment, an engineer can carry out modelling through graphical procedure. The ability to carry out graphical programming makes Simulink
Table 2: Truth table for Equation1 1Equation 1
Table 3: Sample input for equation 2
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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superior to its companion, MATLAB (Karris, 2006). This is because the design engineer can focus his attention more on conceptualization of the design, than the syntax.
The snapshot in Figure 2 below shows the Simulink environment.
As can be seen from the snapshot in Figure 2, the Simulink environment has many libraries, each of which is loaded with a lot of functions for effective engineering design and simulation.
To use the design in Simulink, we click on the New Model button, as shown Figure 3.
Clicking the New model button will launch a design entry interface (Figure 4), in which we can design the magnitude comparator.
Figure 2: Snap Shot of Simulink Environment
Figure 3: Starting a new model in Simulink
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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2.4 Design implementation
Employing Simulink and using equations 1, 2, and 3, the design of the 4-bit magnitude comparator is presented in Figure 5 below:
Figure 5: A 4-bit magnitude comparator using Simulink
Figure 4: Design entry interface
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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The design shown in Figure 5 is divided into three parts: the input stage, the combination stage, and output stage. The input stage produces the input signals (4-bit wide), with their corresponding complements, as shown in Figure 6 below:
The combination stage is made of OR and AND gates; this is because the equations used in the design of the 4-bit magnitude comparator involve logical OR and AND operations (Figure 7).
The third and final stage of the comparator circuit is the output stage. This stage, using the Display function block of Simulink displays the simulation results of the comparator circuit (Figure 8).
Figure 6: Input stage of magnitude comparator circuit
Figure 7: Combination stage of magnitude comparator circuit
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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3. Results and discussion
To test and verify the accuracy of the 4-bit magnitude comparator, we simulate it with three set of values, for when A=B, A>B, and A<B. The three set of data are presented in Table 4 a, b and c below:
Table 4: Three sets of data used in simulating the 4-bit magnitude comparator
Figure 9 shows that the output of the magnitude comparator is asserted for the display A=B because the two values being compared are, equal in magnitude.
when A=B:
Figure 10 shows the output of the magnitude comparator being asserted for the display A>B because for the two values being compared A is greater than B.
when A>B:
Figure 11 shows the output of the magnitude comparator being asserted for the display A<B because for the two values being compared A is less than B.
Figure 9: Comparator output when A=B
Figure 10: Comparator output when A>B
Figure 8: Output stage of magnitude comparator
Dibal: Design of a 4-Bit Magnitude Comparator using Simulink. AZOJETE, 9: 9-16, 2013
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when A<B:
4. Conclusion
Based on equations 1, 2 and 3, a 4-bit magnitude comparator was effectively and correctly designed using Simulink. The simulation of the comparator was carried out successfully and the results obtained were as expected. Therefore, the objective of designing the 4-bit magnitude comparator has been achieved.

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