Which of the following statements about design of a hardwired control unit for a

Question

Which of the following statements about design of a hardwired control unit for a CPU is WRONG?

Output of the Decoder corresponding to the last state of Fetch cycle serves as the LOAD (LD) input of the Counter.

There is only one unique input to the Counter (i.e., mapping function of the values of the Instruction Register (IR)) for the Control Unit for a CPU.

Outputs of the Decoder corresponding to the last state of each executive (branch) routine serve as the CLEAR (CLR) input of the Counter values so the execution is moved to the Fetch cycle.

Sequential Counter values are generally assigned to sequential states of the state diagram.

Output of the Decoder corresponding to the last state of Fetch cycle serves as the LOAD (LD) input of the Counter.

There is only one unique input to the Counter (i.e., mapping function of the values of the Instruction Register (IR)) for the Control Unit for a CPU.

Outputs of the Decoder corresponding to the last state of each executive (branch) routine serve as the CLEAR (CLR) input of the Counter values so the execution is moved to the Fetch cycle.

Sequential Counter values are generally assigned to sequential states of the state diagram.

Explanation / Answer

Since the input is varies to the counter, the counter also do the functionality with respect to the different values.

So the below statement is wrong.

There is only one unique input to the Counter (i.e., mapping function of the values of the Instruction Register (IR)) for the Control Unit for a CPU.

Option B is wrong statement.

2

Outputs of the Decoder corresponding to the last state of each executive (branch) routine serve as the CLEAR (CLR) input of the Counter values so the execution is moved to the Fetch cycle.

Option C is wrong statement

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