(Memory mapped I/O – interrupt) Write a MIPS program to implement the following

Question

(Memory mapped I/O – interrupt) Write a MIPS program to implement the following single digit adder: keyboard input: X+Y= display output: X+Y=Z where X and Y are single digits (such as 2 and 7) and Z is the result (such as 9). Please use keyboard interrupt to read the keyboard input from the receiver data, compute the result Z and use polling (on the transmitter control and transmitter data) to send the output X+Y=Z to the display. To test your code, you need open the MMIO in the simulator. Goto ToolsKeyboard and Display MMIO make sure you press “connect to MIPS” to run your code. Sometimes, it is also helpful to press “reset” on the same screen. Dont forget to store registers when you write MIPS functions To slow down execution in the simulator, slide ”Run speed to max” bar to the left. A detailed sketch of implementation was presented in lecture and will also be sent to you by email.

Explanation / Answer

main:
      li $v0 4
      la $a0 prompt
      syscall


# Register usage:
#            s0            loop counter
#            t0            address of recv_ctrl
#            t1            address of recv_buffer
#            t2            address of trans_ctrl
#            t3            address of trans_buffer
#            t4, t5            temporaries
#            t6            char read from input
#            t7            1 => char in t6

      li      $s0, 3            # loop counter

      li       $t0, 0xffff0000      # recv ctrl
      li      $t1, 0xffff0004      # recv buf
      li       $t2, 0xffff0008      # trans ctrl
      li       $t3, 0xffff000c      # trans buf

# First, read and echo 3 lines of input by polling the IO registers, not through
# interrupts:

      mtc0      $0, $12            # Clear IE bit in Status reg to disable interrupts

l1:
      lw      $t4, 0($t0)      # Wait for receiver ready
      and       $t4, $t4, 1
      beq      $t4, 0, l1

      lw      $t6, 0($t1)      # Read character

l2:
      lw      $t4, 0($t2)      # Wait for transmitter ready
      and      $t4, $t4, 1
      beq      $t4, 0, l2

      sw      $t6, 0($t3)      # Write character

      beq      $t6, 0xa, decr      # New line (nl)
      bne      $t6, 0xd, l1      # Carriage return (cr)

decr:
      add      $s0, $s0, -1      # Decrement line counter
      bne      $s0, 0, l1      # If not zero, get another line

# Second, read and echo 3 lines of input by through interrupts:

      mfc0      $t4, $13
      and      $t4, 0xffff00ff      # Clear IP bits in Cause register
      mtc0      $t4, $13

      li      $s0, 3            # loop counter

      li      $t4, 0x2      # Enable device interrupts
      sw      $t4, 0($t0)
      sw      $t4, 0($t2)

      mfc0      $t4, $12      # Enable interrupts and mask in Status reg
      ori      $t4, $t4, 0xff01
      mtc0      $t4, $12


l3:      b      l3            # Loop waiting for interrupts


# Trap handler. Replaces the standard SPIM handler.

      .ktext 0x80000180
      mfc0      $t4, $13      # Get ExcCode field from Cause reg
      srl      $t5, $t4, 2
      and      $t5, $t5, 0x1f      # ExcCode field
      bne      $t5, 0, exception

# An interrupt:
      and      $t5, $t4, 0x800      # Check for IP3 (HW 1)
      beq      $t5, 0, check_trans

# Receiver interrupt:
      lw      $t5, 0($t0)      # Check receiver ready
      and      $t5, $t5, 1
      beq      $t5, 0, no_recv_ready      # Error if receiver is not ready

      lw      $t6, 0($t1)      # Read character
      li      $t7, 1

      beq      $t6, 0xa, decr2      # New line (nl)
      bne      $t6, 0xd, next      # Carriage return (cr)

decr2:
      add      $s0, $s0, -1      # Decrement line counter

next:
      mfc0      $t4, $13      # Get Cause register
      and      $t4, 0xfffff7ff      # Clear IP3 bit
      mtc0      $t4, $13

check_trans:
      beq      $t7, 0, ret_handler      # No char to write yet

      and      $t5, $t4, 0x400      # Check for IP2 (HW 0)
      beq      $t5, 0, check_loop

# Transmitter interrupt:
      lw      $t5, 0($t2)      # Check transmitter ready
      and      $t5, $t5, 1
      beq      $t5, 0, no_trans_ready

      sw      $t6, 0($t3)      # Write character
      li      $t7, 0

      mfc0      $t4, $13      # Get Cause register
      and      $t4, 0xfffffbff      # Clear IP2 bit
      mtc0      $t4, $13

check_loop:
      bne      $s0, 0, ret_handler      # If line counter not zero, get another line

# Done echoing, so terminate program.
      li      $v0, 10
      syscall                  # syscall 10 (exit)

# Return from handler.
ret_handler:
      mfc0      $t4, $12      # Enable interrupts and mask in Status reg
      ori      $t4, $t4, 0xff01
      mtc0      $t4, $12

      eret                  # return to interrupted instruction

exception:
      li      $v0, 4            # Non-interrupt exception
      la      $a0, other_str      # Print message and ignore
      syscall
      b      ret_handler

no_recv_ready:
      li      $v0, 4            # Receiver was not ready after interrupt
      la      $a0, no_recv_str      # Print message and ignore
      syscall
      b      ret_handler

bad_int:
      li      $v0, 4            # Interrupt was not from recv or trans
      la      $a0, bad_int_str      # Print message and ignore
      syscall
      b      ret_handler

no_trans_ready:
      li      $v0, 4            # Transmitter was not ready after interrupt
      la      $a0, no_trans_str      # Print message and ignore
      syscall
      b      ret_handler

      .data
other_str:
      .asciiz "Non-interrupt exception "
no_recv_str:
      .asciiz "Receiver not ready "
no_trans_str:
      .asciiz "Transmitter not ready "
bad_int_str:
      .asciiz "Unknown interrupt "

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