For each problem, list all references used or students consulted (see ECE 118 Co

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For each problem, list all references used or students consulted (see ECE 118 Collaboration Policy on Blackboard) Turn this homework in digitally through Blackboard as a single PDF file. Feel free to either use a word processing system to create your PDF, write on the paper, and then scan or take a picture to create a PDF to turn into Blackboard. What is an interrupt? Briefly explain how the PIC16 responds to an interrupt. Write the interrupt vector table code which will execute a subroutine called TMR0_ISR if the interrupt was caused by a timer_0 overflow interrupt, execute a subroutine called TXU_ISR if the interrupt was caused by the USART transmit interrupt, and return from the interrupt if neither of these two interrupts caused the interrupt What it the address of the first instruction of your interrupt vector table code? Write a complete initialization subroutine which will correctly set and initialize PORT C2 and PORT Cl as an input and PORT C7 as an output, as well as enabling the oscillator fail peripheral interrupt. What is the purpose of the Latch Register? Briefly explain how it works and when it is used. Write the configuration directives to set CONFIG1 and CONFIG2 to the default settings discussed in lecture 15, but modify it enable the software WDT. disable clock-out, enable reset on stack over/under-flow, and use the low-power oscillator as the system clock. Use hex for your answer, and make sure to show your work. Briefly explain what the Watchdog Tuner is, and give an example of why a programmer might want to use it

Explanation / Answer

Answers ::

(1)

Interrupt ::
Interrupt is a signal from a device attached to computer (or) from a program within the computer which requires operating system to stop and figure out what to do next.
  
   If we implemented in hardware,interrupt controller circuit such as the IBM PC Programmable Interrupt Controller [PIC] may be connected between interrupting device and the the processor's interrupt pin to multiplex several sources of interrupt onto one (or) two CPU lines typically available.
  
Interrupts are categorized into different types ::

Maskable interrupt (IRQ): it is a hardware interrupt which may be ignored by setting a bit in interrupt mask register bit-mask.
Non maskable interrupt (NMI):it is a hardware interrupt which lacks an associated bit mask so that it can never be ignored.
Inter processor interrupt (IPI):it is a special case of interrupt which is generated by one processor to interrupt the other processor in a multiprocessor system.
Software interrupt:it is an interrupt generated within a processor by executing an instruction.
Spurious interrupt:it is a hardware interrupt which is unwanted.

Processors typically have internal interrupt mask which allows software to ignore all the external hardware interrupts while it is set. Setting (or) clearing this mask may faster than the accessing an interrupt mask register in a PIC (or) disabling interrupts in the device itself.

Interrupt which leaves the machine in a well defined state is called 'precise interrupt'.This type of interrupt has four properties:

1.Program Counter is saved in a known place.
2.All the instructions before the one pointed to by the Program Counter have fully executed.
3.No instructions beyond the one pointed to by the Program Counter has been executed
4.Execution state of the instruction pointed to by the Program Counter is known.

(4)

latch is a circuit which has two stable states and be used to store the state information.

The problem is due to 'read-modify-write' effect.
It is most commonly encountered when we use BSF (or) BCF instructions directly on the PORT registers, because these instructions read current state of the port pins, modify one bit and then re-write the entire port.
If pin state is does not match the latch, then we will get unexpected results i.e., bits changing other than the one we wanted to change.

(6)

A watchdog timer is a hardware timer which automatically generates a system reset,if the main program neglects to periodically service it,which is often used to automatically reset an embedded device which hangs because of software (or) hardware fault.

Watchdog timers are found in embedded systems and other computer controlled equipment where humans cann't easily access equipment (or) would be unable to react to faults in timely manner. In this types systems,computer cannot depend on human to reboot it if it is hangs,it must be self reliant.

There are two stages : 1. Single-stage watchdog
2. Multi-stage watchdog

Time intervals :
Watchdog timers have either fixed (or) programmable time intervals. Some watchdog timers allow time interval to be programmed by selecting from among few selectable, discrete values. The interval can be programmed to be arbitrary values.       

Watchdog timer is a piece of the hardware which can be used to automatically detect the software anomalies and reset the processor if any occur.A watchdog timer is based on counter which counts down from some initial value to the zero. Embedded software selects the counter initial value and periodically restarts it. If the counter ever reaches the count zero before software restarts it,the software is presumed to be malfunctioning and processor's reset signal is asserted. Processor will be restarted as if human operator had cycled the power.      

/// *** Thank You *** ///

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